You can design and simulate algorithms using MATLAB, Simulink, and Stateflow, then generate code for Xilinx FPGAs and Xilinx® Zynq®-7000 SoCs using HDL Coder. In Xilinx System Generator for DSP, you can generate HDL code for Xilinx FPGAs using Xilinx-specific blocks, and you can use HDL Coder to generate code from Simulink models containing both native Simulink blocks and Xilinx-specific blocks.
Using HDL Coder, you can automatically generate VHDL and Verilog code for Xilinx FPGAs from MATLAB, Simulink, and Stateflow models. This approach supports a variety of system objects available in products such as Communications System Toolbox and DSP System Toolbox.
With HDL Coder and Xilinx Vivado or ISE® Design Suite, you can automatically synthesize your design and program the bitstream on your selected FPGA board. HDL Coder generates a VHDL test bench for functional verification. Additionally, HDL Coder outputs highly traceable code for applications that must adhere to certification standards such as DO-254.
HDL Coder can generate target-specific HDL code with Xilinx LogiCORE ® IP. The Xilinx Floating-Point Operator core supports a set of floating-point arithmetic functions optimized for synthesis on Xilinx FPGAs. Mapping to the Xilinx FPGA target-specific floating-point library enables you to synthesize your floating-point design without requiring floating-point to fixed-point conversion. This approach offers several advantages:
HDL Coder supports code generation for Simulink models constructed with a combination of blocks from Simulink and Xilinx-specific blocksets from System Generator. The System Generator Subsystem block in HDL Coder enables you to include models built with System Generator in Simulink as subsystems. HDL Coder uses System Generator to generate code from the subsystem blocks and integrates the complete design into synthesizeable HDL.
This approach enables you to:
With Model-Based Design, design teams can simulate models for complete systems and use C/C++ and HDL code generation from Simulink to target Xilinx Zynq-7000 All Programmable SoC devices, which offer combination of ARM® Cortex®-A9 cores along with the programmable logic of a conventional Xilinx FPGA.
In this hardware/software workflow, you generate C/C++ with Embedded Coder® for your software model, and can use HDL Coder to generate Verilog and VHDL to produce IP cores from your hardware model. Using optimizations provided with the coders, you customize generated code for your target Zynq SoC. For example, you can use resource sharing and distributed pipelining from HDL Coder to improve the efficiency of your FPGA implementation. Similarly, you can use configuration options and processor-specific optimizations provided with Embedded Coder to improve MCU and DSP execution performance on ARM Cortex-A9 cores. For NEON™-optimized code for DSP filters, you can use the ARM Cortex-A Ne10 Library Support from DSP System Toolbox.
Using Embedded Coder and HDL Coder support packages for Zynq, you integrate generated C/C++ and HDL code into your implementation, use Xilinx Vivado or ISE for synthesis and place and route, and target your selected SoC. Fully automated workflows are available for supported Zynq boards, and address applications such as motor control, video/image processing, and software-defined radio.
With HDL Verifier, you can verify code using your MATLAB or Simulink model as a system-level test bench and cosimulating generated code with HDL simulators from Mentor Graphics® or Cadence®. You can perform FPGA-in-the-loop verification using your model again as a system-level test bench and executing generated code on actual Xilinx FPGA boards.
HDL Coder and HDL Verifier provide an integrated environment for generating, programming, and verifying HDL implementations for FPGAs.