Fujitsu Develops and Tests State-of-the-Art 40 Gbps Optical Transponder


Develop a 40 Gbps serializer/deserializer integrated circuit for an optical transponder


Use Simulink to model and simulate key components of the design, and use MATLAB and Instrument Control Toolbox to automate chip testing and characterization


  • First-silicon-success for components verified in Simulink
  • Faster verification of mixed-signal designs
  • Test time reduced by 90%

“By including circuit-level simulation results in our Simulink models we can simulate millions of cycles with the accuracy needed to account for noise and other transient effects. Simulink is the only tool fast enough for our jitter-tolerance simulations.”

William Walker, Fujitsu Laboratories of America
SERDES chips mounted on inert substrate for testing.

To keep up with mounting network traffic, telecom carriers and cable operators worldwide use optical networking solutions from Fujitsu Laboratories of America.

In response to the demand for higher data rates, Fujitsu designed, simulated, and tested 40 Gbps serializer/deserializer (SERDES) chips using MathWorks tools.

“Simulink enabled us to incorporate the results from sub-picosecond SPICE simulations into high-level simulations, modeling millions of symbols,” explains William Walker, a Fujitsu Laboratories of America vice president. “Later, with MATLAB and Instrument Control Toolbox we automated and accelerated the process of testing and characterizing the devices implemented in silicon.”


Fujitsu wanted the SERDES to consume no more than 4.5 watts; comparable systems consume 12 watts. This stringent power requirement led Fujitsu to switch from bipolar to CMOS technology for the SERDES chip. “While CMOS technology uses less power, it is typically slower than bipolar, and there is more process variation,” says Nikola Nedovic, a Fujitsu researcher. “As a result, designing with CMOS is much more difficult at the bandwidth and high data rates we are working with, making system modeling crucial to our success.”

Fujitsu needed highly accurate circuit simulations, but circuit emulators cannot handle the millions of symbols needed to simulate the effects of jitter and measure bit error rate (BER). “SPICE can simulate a few hundred symbols, but much more than that and the simulations become too slow,” says Nedovic.

Once the chip was fabricated, the engineers would need to thoroughly characterize and verify the device with a minimum of manual steps.


Fujitsu engineers used Simulink® to model and simulate the SERDES chips and MATLAB® and Instrument Control Toolbox™ to automate testing of the hardware prototypes.

In order to simulate the large amounts of data passing through the system, they modeled the most complex subsystems in the SERDES design—the clock and data recovery (CDR) unit and the limiting amplifier (LA)—in Simulink.

The engineers used SPICE and other circuit emulators to simulate the individual analog blocks that make up the CDR and LA. They then abstracted the detailed results from the SPICE simulations into Simulink blocks to create a much faster, higher-level representation.

For example, to model jitter in the voltage controlled oscillator (VCO), the team first used advanced circuit analysis tools to simulate 1/f noise in each transistor and thermal noise in each resistor. In Simulink they created an ideal model of the VCO, inserted noise sources, and adjusted the noise level until the Simulink model produced results that matched the circuit-level simulations.

The engineers assembled complete models of the CDR and LA and then used Simulink to simulate the millions of cycles needed to gauge BER and assess the performance of nonlinear subsystems. The Simulink models ran much faster than the circuit-level models, enabling them to simulate millions of symbols in a reasonable time frame.

After laying out the integrated circuit, the engineers reran their circuit-level simulations using the post-layout netlist. They could then measure second-order parasitic capacitive and resistance effects not accounted for in the preliminary design. They incorporated these effects into the Simulink models and reran simulations before sending the design to be fabricated.

Design verification test engineers wrote MATLAB scripts to automate the testing process. Using Instrument Control Toolbox, they controlled signal generators and collected data from spectrum, vector network, and communication signal analyzers. The scripts were also used to control on-chip built-in BER test circuits.

Modeling engineers characterized individual devices such as inductors, varactors, and field-effect transistors (FETs) using MATLAB. The engineers used this data to further improve the accuracy of their simulations by refining the device models used by SPICE simulators.

The final SERDES ICs consume just 3.5 watts—well below the initial power goal of 4.5 watts.


  • First-silicon-success for components verified in Simulink. “When we respin a chip, the costs can be up to $1 million,” says Walker. “Though there were some re­spins on this project, the subsystems that we simulated using Simulink—the CDR and the LA—were right the first time.”

  • Faster verification of mixed-signal designs. “We needed to ensure a BER of less than 1 bit per trillion, and at 40 Gbps, that cannot be done with circuit-level or hardware-description-level simulators,” says Nedovic. “With Simulink we simulated millions of cycles to measure BER and verified much of the design before fabricating our first chips.”

  • Test time reduced by 90%. “If we characterized FETs and other devices using manual tests instead of MATLAB scripts, it would take 10 times longer to get all the data we need,” says Walker. “Tests that require a full day to complete by hand can be completed in minutes—and the automated tests are more consistent.”