FIR Decimator
Finite impulse response (FIR) decimation filter
Libraries:
DSP HDL Toolbox /
Filtering
Description
The FIR Decimator block implements a single-rate polyphase FIR decimation filter that is optimized for HDL code generation. The block provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the block models architectural latency including pipeline registers and resource sharing.
The block accepts scalar or vector input. When you use vector input and the vector size is less than the decimation factor, the decimation factor must be an integer multiple of the vector size. In this case, the output is scalar and an output valid signal indicates which samples are valid after decimation. The output data is valid every DecimationFactor/VectorSize samples. The waveform shows an input vector of four samples and a decimation factor of eight. The output data is a scalar that is valid every second cycle.
When you use vector input and the vector size is greater than the decimation factor, the vector size must be an integer multiple of the decimation factor. In this case, the output is a vector of VectorSize/DecimationFactor samples. The waveform shows an input vector of eight samples and a decimation factor of four. The output data is a vector of two samples on every cycle.
The block provides two filter structures. The direct form systolic architecture provides an implementation that makes efficient use of Intel® and Xilinx® DSP blocks. This architecture can be fully parallel or serial. To use a serial architecture, the input samples must be spaced out with a regular number of invalid cycles between the valid samples. The direct form transposed architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.
For scalar input, all filter structures optimize hardware resources by sharing multipliers for symmetric or antisymmetric filters and by removing the multipliers for zero-valued coefficients such as in half-band filters and Hilbert transforms. When your input is a vector, the filter structure removes the multipliers for zero-valued coefficients but does not optimize for symmetric coefficients.
The block implements one filter for each sample in the input vector. The block then shares this filter between the polyphase subfilters by interleaving the subfilter coefficients in time.
Note
The output of the FIR Decimator block does not match the output of the FIR Decimation block from DSP System Toolbox™ sample-for-sample. This difference is mainly because of the phase in which the samples are applied across the subfilters. To match the FIR Decimation block, apply Decimation factor – 1 zeros to the FIR Decimator block at the start of the data stream.
The DSP System Toolbox block also uses slightly different default data types than the DSP HDL Toolbox™ block.
Note
You can also generate HDL code for this hardware-optimized algorithm, without creating a Simulink® model, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the Simulink block.
Examples
FIR Decimation for FPGA
Decimate streaming samples using a hardware-friendly polyphase FIR filter.
Implement Digital Downconverter for FPGA
Design a digital downconverter (DDC) for LTE on FPGAs.
Programmable FIR Filter for FPGA
Implement a programmable FIR filter for hardware and load the filter coefficients by using a memory-style interface.
Ports
Input
Input data must be a real- or complex-valued scalar or vector. When you use vector input and the vector size is less than the decimation factor, the decimation factor must be an integer multiple of the vector size. When you use vector input and the vector size is greater than the decimation factor, the vector size must be an integer multiple of the decimation factor. The vector size must be less than or equal to 64.
When the input data type is an integer type or a fixed-point type, the block uses fixed-point arithmetic for internal calculations.
The software supports double and
single data types for simulation, but not for HDL code generation.
Data Types: fixed point | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes
Control signal that indicates if the input data is valid.
When valid is 1
(true), the block captures the
values from the input data port. When
valid is 0
(false), the block ignores the
values from the input data
port.
Data Types: Boolean
Since R2025a
Filter coefficients, specified as a row vector of real or complex values. You can change the input coefficients at any time. The size of the coefficient vector must match the size of the sample coefficients specified in the Coefficients prototype parameter. The prototype specifies a sample coefficient vector that is representative of the zero-valued locations of the expected input coefficients. The block uses the prototype to optimize the filter by removing multipliers for zero-valued coefficients.
If the input data is a fixed-point type, the coeff values must also be of a fixed point type. If the input data is a floating-point data type, the coeff values must be of the same data type.
The software supports double and
single data types for simulation, but not for HDL code generation.
Dependencies
To enable this port, set Coefficients
source to Input port
(Parallel interface).
Data Types: fixed point | int8 | int16 | int32 | uint8 | uint16 | uint32 | single | double
Since R2026a
Filter coefficients, specified as a real or complex scalar value to write to internal memory. To load a single coefficient value to internal memory, specify a coeff value with a corresponding address on the caddr port and an enable signal on the cwren port. You can change the input coefficients at any time.
While you write new coefficients into memory, the block
ignores any input data, but still returns
dataOut with
validOut until it clears the
filter pipeline. The block resumes accepting input the
cycle after cdone is set to
1 (true).
The coefficient memory has the same number of addresses as the size of the Coefficients prototype parameter. The prototype specifies a sample coefficient vector that is representative of the zero-valued locations of the expected input coefficients. When you use scalar input data, the block uses the prototype to optimize the filter by sharing multipliers for symmetric or antisymmetric coefficients, and by removing multipliers for zero-valued coefficients. You must write the entire set of coefficients to memory, including symmetric or zero-value coefficients. For example, if you set the Coefficients prototype parameter to a symmetric 14-tap filter, you must write 14 values to the memory interface.
When you use frame-based input data, the block does not optimize the filter for coefficient symmetry. The block still uses the Coefficients prototype parameter to remove multipliers for zero-valued coefficients. The coefficient memory has the same number of locations as the size of the prototype.
If the input data is a fixed-point type, the coeff values must also be of a fixed point type. If the input data is a floating-point data type, the coeff values must be of the same data type.
The software supports double and
single data types for simulation, but not for HDL code generation.
Dependencies
To enable this port, set Coefficients
source to Input port
(Memory interface).
Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | fixed point
Since R2026a
Specify the filter coefficient address as a scalar integer value represented as an unsigned fixed-point type with zero fractional bits. The block derives the size of this integer value, and the size of the internal memory, from the number of unique coefficients in the Coefficients prototype parameter value.
Dependencies
To enable this port, set Coefficients
source to Input port
(Memory interface).
Data Types: fixdt(0,N,0)
Since R2026a
Set this input to 1
(true) to write the value on the
coeff port into the
caddr location in internal
memory.
Dependencies
To enable this port, set Coefficients
source to Input port
(Memory interface).
Data Types: Boolean
Since R2026a
Set this input to 1
(true) to indicate that writing
coefficients to memory is complete. You can set this input
to 1 (true) along
with the last coefficient write, or on a later cycle with
no active write.
Dependencies
To enable this port, set Coefficients
source to Input port
(Memory interface).
Data Types: Boolean
Control signal that clears internal states. When
reset is 1
(true), the block stops the
current calculation and clears internal states. When the
reset is 0
(false) and the input
valid is 1
(true), the block captures data
for processing.
For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.
Dependencies
To enable this port, on the Control Ports tab, select Enable reset input port.
Data Types: Boolean
Output
Parameters
Algorithms
The block implements a polyphase filter bank where the filter coefficients are decomposed into DecimationFactor subfilters. If the filter length is not divisible by the Decimation factor parameter value, then the block zero-pads the coefficients. When your input is regularly spaced, with two or more cycles between valid samples, as indicated by the Minimum number of cycles between valid input samples parameter, the filter can share multiplier resources in time.
This flow chart shows which filter architectures result from your parameter settings. It also shows the number of multipliers used by the filter implementation. The filter architecture depends on the input frame size, V, the decimation factor, R, the number of cycles between valid input samples, N, and the number of filter coefficients, L. The architectures are in order from lowest resource use on the left, to higher resources on the right. The higher resource architectures are trading off resource use for higher throughput. Each architecture is described below the flow chart.
If the filter is symmetric and you select
Optimize symmetric coefficients, the architecture
shares multipliers for matching coefficients. In that case the number of filter
coefficients, L, in the flow chart represents
NumCoeffs/2. This option is
supported only with scalar input. (since R2024b)
The number of multipliers shown in the flow chart is for filters with real input and real coefficients. For complex input, the filter uses three times as many multipliers.
Architecture 1 — Fully parallel one-tap interleaved polyphase filter bank.
When DecimationFactor is greater than the filter length, for any value of NumCycles, the filter becomes a single-tap fully parallel systolic filter with interleaved coefficients, and uses a single multiplier.
For this architecture, the latency displayed on the block is the number of cycles between the first valid input and the first valid output, assuming the input is contiguous. The latency is longer than displayed if there are invalid cycles between valid input samples, because the fully parallel systolic filter requires new valid input samples to advance the pipeline.
Architecture 2 — Single fully serial filter.
When the filter has NumCycles greater than the number of filter coefficients, the block implements a single fully serial filter and decimates the output samples by the decimation factor. This serial filter uses one multiplier.
Architecture 3 — Partly serial polyphase filter bank.
When the filter has NumCycles greater than one and less than the number of filter coefficients, the block implements a polyphase filter with DecimationFactor subfilters. This diagram shows input data with a valid sample every second cycle and a DecimationFactor of
4. The output data has one valid sample every eight cycles. This filter implementation uses FilterLength/NumCycles multipliers.
Architecture 4 — Fully parallel polyphase interleaved filter bank (scalar).
The diagram shows the polyphase filter bank with scalar input, DecimationFactor set to
4, and NumCycles set to1. The four sets of decomposed coefficients are interleaved in time over a single subfilter. The output data sample is valid every four cycles. The filter uses FilterLength/DecimationFactor multipliers.
When you select Optimize symmetric coefficients, the decomposed sets of coefficients may not have the same symmetry and zero locations, which means the architecture cannot share the subfilter. In this case, the filter uses architecture 3, where each set of coefficients has its own subfilter. The output of architecture 3 can differ from architecture 4 by one LSB.
Architecture 5 — Fully parallel polyphase interleaved filter bank (vector)
The diagram shows the polyphase filter bank for an input vector size smaller than the decimation factor. This filter has an input vector of four values and DecimationFactor is set to 8. Each of the four subfilters has two sets of coefficients interleaved in time. The filter uses InputSize*FilterLength/DecimationFactor multipliers.
Architecture 6 — Fully parallel frame-based filter bank
With an input vector size greater than the decimation factor, the block implements decimation factor subfilters, each with frame-based input of VectorSize/DecimationFactor samples. The output vector has VectorSize/DecimationFactor samples. The filter uses InputSize*FilterLength/DecimationFactor multipliers.
Each subfilter is implemented with a Discrete FIR Filter block. The adder at the output is pipelined to accommodate higher synthesis frequencies. For architecture details, see FIR Filter Architectures for FPGAs and ASICs.
