Delay between two sampling phases
Select the minimum delay that separates two ADC conversions in interleaved mode
Since R2024b
Model Configuration Pane: Hardware Implementation / Simulink or Embedded Coder Hardware Support Package / Hardware board settings / Target hardware resources / ADC Common
Description
The Delay between two sampling phases parameter offers the option to select the minimum delay that separates two ADC conversions in interleaved mode.
Settings
5 * T_ADCCLK
(default) |
6 * T_ADCCLK
|
7 * T_ADCCLK
|
8 * T_ADCCLK
|
9 * T_ADCCLK
|
10 * T_ADCCLK
|
11 * T_ADCCLK
|
12 * T_ADCCLK
|
13 * T_ADCCLK
|
14 * T_ADCCLK
|
15 * T_ADCCLK
|
16 * T_ADCCLK
|
17 * T_ADCCLK
|
18 * T_ADCCLK
|
19 * T_ADCCLK
|
20 * T_ADCCLK
The option to select the minimum delay that separates two ADC conversions in interleaved mode.
Recommended Settings
No recommendation.
Programmatic Use
No programmatic use is available. |
Version History
Introduced in R2024b