Specify Xilinx Vivado exported block design Tcl file
the exported block design Tcl file that contains the Xilinx® Vivado® embedded
system design. Use this method if your synthesis tool is Xilinx Vivado.
bd_tcl_file — Block design Tcl file
Block design Tcl file that you exported from your Xilinx Vivado embedded system design project, specified as a character vector. The Tcl file name must be the same as the Vivado block diagram name.
If you have more than one AXI Master IP, in the custom block design Tcl file, you must make sure that the AXI Master IPs connect to the same AXI Interconnect IP. The AXI4 slave interfaces in the HDL IP core also connect to this Interconnect.
If your synthesis tool is Xilinx ISE, use the
If your synthesis tool is Altera® Quartus II, use the
Introduced in R2015a