Clock Settings and Timing Controller Postfix Parameters

This page describes configuration parameters that reside in the Clock settings section of the HDL Code Generation > Global Settings pane of the Configuration Parameters dialog box. Use these parameters to specify the clock signal name, the number of clock inputs, the active clock edge, and the postfix for the clock process and the timing controller.

Clock input port

Specify the name for the clock input port in generated HDL code.

Settings

Default: clk

Enter the clock signal name in generated HDL code as a character vector.

For a generated entity my_filter, if you specify 'filter_clock' as the clock signal name, the entity declaration is as shown in this code snippet:

ENTITY my_filter IS
   PORT( filter_clock   :  IN  std_logic;
         clk_enable     :  IN  std_logic;
         reset          :  IN  std_logic;
         my_filter_in   :  IN  std_logic_vector (15 DOWNTO 0); -- sfix16_En15
         my_filter_out  :  OUT std_logic_vector (15 DOWNTO 0); -- sfix16_En15
         );
END my_filter;

If you specify a VHDL^®, Verilog^® or SystemVerilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL, Verilog or SystemVerilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.

Command-Line Information

Property: ClockInputPort

Type: character vector

Value: A valid identifier in the target language

Default: 'clk'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockInputPort','system_clk')
makehdl('sfir_fixed/symmetric_fir')
```

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','ClockInputPort','system_clk')

Clock inputs

Specify generation of single or multiple clock inputs.

Settings

Default: Single

Single

Generates a single clock input for the DUT. If the DUT is multirate, the input clock is the primary clock rate, and a timing controller is synthesized to generate additional clocks as required. It is recommended that you use a single clock signal in your design.

Multiple

Generates a unique clock for each Simulink^® rate in the DUT. The number of timing controllers generated depends on the contents of the DUT. The oversample factor must be 1 (default) to specify multiple clocks.

For a multirate model, to generate clock for each Simulink rate, make sure to include sequential logic block, such as delay block, at each Simulink rate. If the sequential logic is not present for a particular Simulink rate, HDL Coder™ do not generate the clock signal for that rate.

Command-Line Information

Property: ClockInputs

Type: character vector

Value: 'Single' | 'Multiple'

Default: 'Single'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockInputs','Multiple')
makehdl('sfir_fixed/symmetric_fir')
```

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','ClockInputs','Multiple')

Clock edge

Specify the active clock edge that triggers Verilog or SystemVerilog always blocks or VHDL process blocks in the generated HDL code.

Settings

Default: Rising.

Rising: The rising edge, or 0-to-1 transition, is the active clock edge.
Falling: The falling edge, or 1-to-0 transition, is the active clock edge.

Command-Line Information

Property: ClockEdge

Type: character vector

Value: 'Rising' | 'Falling'

Default: 'Rising'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockEdge','Falling')
makehdl('sfir_fixed/symmetric_fir')
```

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','ClockEdge','Falling')

Clocked process postfix

Specify the postfix as a character vector. The code generator appends this postfix to HDL clock process names.

Settings

Default: _process

HDL Coder uses process blocks for register operations. The label for each of these blocks is derived from a register name and the postfix _process. For example, the code generator derives the label delay_pipeline_process in the following block declaration from the register name delay_pipeline and the default postfix _process.

delay_pipeline_process : PROCESS (clk, reset)
BEGIN
  .
  .
  .

Command-Line Information

Property: ClockProcessPostfix

Type: character vector

Default: '_process'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockProcessPostfix','delay_postfix')
makehdl('sfir_fixed/symmetric_fir')
```

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir','ClockProcessPostfix','delay_postfix')

Timing controller postfix

Specify the postfix as a character vector. The code generator appends this suffix to the DUT name to form the timing controller name.

Settings

Default: '_tc'

A timing controller file is generated if the design uses multiple rates, for example:

When code is generated for a multirate model.
When an area or speed optimization, or block architecture, introduces local multirate.

The timing controller name is based on the name of the DUT. For example, if the name of your DUT is my_test, by default, HDL Coder adds the postfix _tc to form the timing controller name, my_test_tc.

Command-Line Information

Property: TimingControllerPostfix

Type: character vector

Default: '_tc'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.