You can add a Tcl script that configures your synthesis project.
To configure your synthesis project using a Tcl script:
Create a Tcl script that contains commands to customize your synthesis project.
For example, to specify the finite state machine style:
For Xilinx® ISE, create a Tcl script that contains the following line:
project set "FSM Encoding Algorithm" "Gray" -process "Synthesize - XST"
For Xilinx Vivado®, create a Tcl script that contains the following line:
set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION gray [get_runs synth_1]
In the HDL Workflow Advisor, in the FPGA Synthesis and Analysis > Create Project task, in the Additional source files field, enter the full path to the Tcl file manually, or by using the Add button.
When HDL Coder™ creates the project, the Tcl script is executed to apply the synthesis project settings.