Constrained Output Pipelining
What Is Constrained Output Pipelining?
With constrained output pipelining, you can specify a nonnegative number of registers at the outputs of a block.
Constrained output pipelining does not add registers, but instead redistributes existing delays within your design to try to meet the constraint. If HDL Coder™ cannot meet the constraint with existing delays, it reports the difference between the number of desired and actual output registers in the timing report.
Distributed pipelining does not move registers you specify with constrained output pipelining.
When to Use Constrained Output Pipelining
Use constrained output pipelining when you want to place registers at specific locations in your design. This can enable you to optimize the speed of your design.
For example, if you know where the critical path is in your design and want to reduce it, you can use constrained output pipelining to place registers at specific locations along the critical path.
Requirements for Constrained Output Pipelining
Your design must contain existing delays or registers. When there are fewer registers than HDL Coder needs to satisfy your constraint, the coder reports the difference between the number of desired and actual output registers.
You can add registers to your design using input or output pipelining.
Specify Constrained Output Pipelining
To specify constrained output pipelining for a block using the UI:
In the Apps tab, select HDL Coder. The HDL Code tab appears. Select the Subsystem and then click HDL Block Properties. For ConstrainedOutputPipeline, enter the number of registers you want at the output ports.
Right-click the block and select HDL Code > HDL Block Properties. For ConstrainedOutputPipeline, enter the number of registers you want at the output ports.
To specify constrained output pipelining, on the command line, enter:
subsys, in your model,
Limitations of Constrained Output Pipelining
HDL Coder does not constrain output pipeline register placement:
Within a DUT subsystem, if the DUT contains a subsystem, model reference, or model reference with black box implementation.
At the outputs of any type of delay block or the top-level DUT subsystem.