Frame to Sample Conversion Parameters

You can use the configuration parameters in the Frame to Sample Conversion tab of the HDL Code Generation > Optimization pane of the Configuration Parameters dialog box to convert matrix inputs to smaller sized samples to reduce the amount of I/O that handles large input signals for HDL code generation.

Enable frame to sample conversion

Select this parameter to enable frame-to-sample conversion. If your model is not synthesizable because it requires a large amount of I/O, this optimization can reduce the I/O in the design and generate synthesizable HDL code. The frame-to-sample conversion converts matrix inputs to smaller samples by streaming the input signal for HDL code generation to reduce the I/O that handles a large input signal.

Settings

Default: Off

On

Stream input signals attached to Inport blocks that have the HDL block property ConvertToSamples enabled.

Off

Do not stream input signals.

Dependency

Enable the HDL block property ConvertToSamples for at least one Inport block on your DUT that has an incoming matrix signal to be streamed.

Command-Line Information

Property: FrameToSampleConversion

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the FrameToSampleConversion setting when you generate HDL code for a DUT subsystem in a model using either of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl('<model_name/DUT_name>', ... 
          'FrameToSampleConversion','on')

• When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.

  hdlset_param('<model_name','FrameToSampleConversion','on')
  makehdl('<model_name/DUT_name>')

See Also

• makehdl

• HDL Code Generation from Frame-Based Algorithms

Samples per cycle

Use this parameter to specify the size of the signals after the frame-to-sample conversion streams them. The streamed input signal is either a scalar (one sample per cycle) or 1-D vectors with N elements (N samples per cycle).

Settings

Default: 1

Enter an integer with a value greater than or equal to one. When you use the default value, the streamed input signal is one sample per cycle or a scalar signal. When you use an integer N, where N is an integer greater than one, the streamed input signal is N samples per cycle or a 1-D vector with N elements.

Dependency

To enable this parameter, select Enable frame to sample conversion.

Command-Line Information

Property: SamplesPerCycle

Type: integer

Value: integer greater than or equal to 1

Default: 1

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the SamplesPerCycle setting when you generate HDL code for a DUT subsystem in a model using either of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl('<model_name/DUT_name>', ... 
          'SamplesPerCycle',2)

• When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.

  hdlset_param('<model_name>','SamplesPerCycle',2)
  makehdl('<model_name/DUT_name>')

See Also

• makehdl

Input FIFO size

Use this parameter to specify the register size of the generated input FIFOs around the streaming matrix partitions. The frame-to-sample conversion generates an input FIFO for every input port in the DUT that has a streaming matrix input signal. The Input FIFO size parameter must be greater than equal to four, the minimum size of the HDL FIFO block.

Settings

Default: 10

Dependency

To enable this parameter, select Enable frame to sample conversion.

Command-Line Information

Property: InputFIFOSize

Type: integer

Value: integer greater than or equal to 4

Default: 10

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the InputFIFOSize setting when you generate HDL code for a DUT subsystem in a model using either of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl('<model_name/DUT_name>', ... 
          'InputFIFOSize',20)

• When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.

  hdlset_param('<model_name>','InputFIFOSize',20)
  makehdl('<model_name/DUT_name>')

See Also

• makehdl

• HDL FIFO

Output FIFO size

Use this parameter to specify the register size of the generated output FIFOs around the streaming matrix partitions. The frame-to-sample conversion generates an output FIFO for every output port in the DUT that is connected to a streaming matrix output signal. The Output FIFO size parameter must be greater than equal to four, the minimum size of the HDL FIFO block.

Settings

Default: 10

Dependency

To enable this parameter, select Enable frame to sample conversion.

Command-Line Information

Property: OutputFIFOSize

Type: integer

Value: integer greater than or equal to 4

Default: 10

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the OutputFIFOSize setting when you generate HDL code for a DUT subsystem in a model using either of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl('<model_name/DUT_name>', ... 
          'OutputFIFOSize',20)

• When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.

  hdlset_param('<model_name>','OutputFIFOSize',20)
  makehdl('<model_name/DUT_name>')

See Also

• makehdl

• HDL FIFO

Input processing order

Use this parameter to choose between row-major and column-major ordering for the frame inputs that the frame-to-sample conversion optimization converts to sample inputs. This setting affects how the data is streamed into the device under test (DUT), but does not change the behavior of the generated DUT.

Settings

Default: RowMajor

RowMajor

Traverse the input frame data for the frame-to-sample conversion using row-major ordering, which traverses the data from left to right and then top to bottom across the frame-based input matrix.

ColumnMajor

Traverse the input frame data for the frame-to-sample conversion using column-major ordering,which traverses the data from top to bottom and then left to right across the frame-based input matrix.

Dependency

To enable this parameter, select Enable frame to sample conversion.

Command-Line Information

Property: InputProcessingOrder

Type: character vector

Value: 'RowMajor' | 'ColumnMajor'

Default: 'RowMajor'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the InputProcessingOrder setting when you generate HDL code for a DUT subsystem in a model using either of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl('<model_name/DUT_name>','InputProcessingOrder','ColumnMajor')

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code by using makehdl.

  hdlset_param('<model_name>','InputProcessingOrder','ColumnMajor')
  makehdl('<model_name/DUT_name>')

See Also

• makehdl

• Optimize Area Usage for Frame-Based Algorithms with Tall Array Inputs

Delay size threshold for external memory (kilobytes)

Use this parameter to specify a threshold size in kilobytes to map large integer delays to input and output DUT ports and offload large delays to external memory outside of your FPGA. Offloading delays to external memory is useful when a design requires an input frame be delayed and operated on and the delays do not fit on the chip block RAM. For example, if your design requires a comparison between two different frames, which creates a large delay, set this threshold parameter to save resources on your FPGA that would otherwise be used to store the delay.

Settings

Default:10000

Enter a threshold value N that is greater than or equal to one to map delays greater than or equal to N to external memory by using input and output DUT ports. When you use the default value 10000, HDL Coder™ maps delays with a register size of 10000 kilobytes or greater to external memory.

Dependency

To enable this parameter, select Enable frame to sample conversion.

Command-Line Information

Property: DelaySizeThreshold

Type: double

Value: double value greater than or equal to 1

Default: 10000

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use DelaySizeThreshold to offload the memory required for a 4k frame, 8250 kilobytes of external memory storage, by setting the DelaySizeThreshold value to 8250 .

You can then use DelaySizeThreshold when you generate HDL code for a DUT subsystem in a model using either of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl('<model_name/DUT_name>', ... 
          'DelaySizeThreshold',8250)

• When you use hdlset_param, set the parameter on the model and then generate HDL code by using the makehdl function.

  hdlset_param('<model_name>','DelaySizeThreshold',8250)
  makehdl('<model_name/DUT_name>')

See Also

• makehdl

• Offload Large Delays from Frame-Based Models to External Memory