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Minimize Clock Enables

By default, HDL Coder™ generates code in a style that is intended to map to registers with clock enables, and the DUT has a top-level clock enable port.

If you do not want to generate registers with clock enables, you can minimize the clock enable logic. For example, if your target hardware contains registers without clock enables, you can save hardware resources by minimizing the clock enable logic.

The following VHDL® code shows the default style of generated code, which uses clock enables. The enb signal is the clock enable:

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        Unit_Delay_out1 <= In1_signed;
      END IF;
    END IF;
  END PROCESS Unit_Delay_process;

The following VHDL code shows the style of code you generate if you minimize clock enables:

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      Unit_Delay_out1 <= In1_signed;
    END IF;
  END PROCESS Unit_Delay_process;

Using the GUI

To minimize clock enables, in the HDL Workflow Advisor, on the HDL Code Generation > Set Code Generation Options > Set Optimization Options > General tab, select Minimize clock enables.

Using the Command Line

To minimize clock enables, in the coder.HdlConfig configuration object, set the MinimizeClockEnables property to true. For example:

hdlCfg = coder.config('hdl')
hdlCfg.MinimizeClockEnables = true;

Limitations

If you specify area optimizations that the coder implements by increasing the clock rate in certain regions of the design, you cannot minimize clock enables. The following optimizations prevent clock enable minimization:

  • Resource sharing

  • RAM mapping

  • Loop streaming