Timing Controller Settings
This page describes parameters that reside in the HDL Code Generation > Global Settings > Coding Style tab of the Configuration Parameters dialog box.
Optimize timing controller
Optimize timing controller entity for speed and code size by implementing separate counters per rate.
HDL Coder™ generates multiple counters (one counter for each rate in the model) in the timing controller code. The benefit of this optimization is that it generates faster logic, and the size of the generated code is usually much smaller.
The coder generates a timing controller that uses one counter to generate all rates in the model.
|Type: character vector|
Timing controller architecture
Specify the architecture of the generated timing controller. HDL Coder generates a timing controller in the DUT if this parameter is set to
a timing controller is required by the design. For example, a timing controller is
required by the design when:
You generate HDL code for a multirate model.
You specify a cascade block implementation for certain blocks.
HDL Coder generates a separate timing controller code file that contains a module that defines timing signals, such as clock, reset, external clock enable inputs and clock enable output. In a multirate model, the timing controller module generates the required rates from a single primary clock using one or more counters and multiple clock enables. For more information, see Timing Controller for Multirate Models.
Generate a timing controller in the DUT without a reset. This setting generates a timing controller code file as its own HDL file and instantiates the timing controller in the DUT at the top level.
Generate a timing controller in the DUT with a reset port. This setting generates a timing controller code file as its own HDL file and instantiates the timing controller in the DUT at the top level. If you select this option, the Clock inputs value must be
Move the timing controller externally and expose the clock enable signals from the top-level design. This setting prevents the creation of a timing controller inside the DUT and does not generate a timing controller code file during HDL code generation, which allows you to integrate your own custom external timing controller into the design. If you select this option, the Clock inputs value must be
When generating a test bench to validate your design, a timing controller file is generated to drive the DUT timing controller inputs for test bench validation. HDL Coder still keeps the clock enable signals exposed at the top-level design for external timing controller integration.
|Type: character vector|