Timing Controller Settings

This page describes parameters that reside in the HDL Code Generation > Global Settings > Coding Style tab of the Configuration Parameters dialog box.

Optimize timing controller

Optimize timing controller entity for speed and code size by implementing separate counters per rate.

Settings

Default: On

On: HDL Coder™ generates multiple counters (one counter for each rate in the model) in the timing controller code. The benefit of this optimization is that it generates faster logic, and the size of the generated code is usually much smaller.
Off: The coder generates a timing controller that uses one counter to generate all rates in the model.

Tip

A timing controller code file is generated if required by the design, for example:

When code is generated for a multirate model
When a cascade block implementation for certain blocks is specified

This file contains a module defining timing signals (clock, reset, external clock enable inputs and clock enable output) in a separate entity or module. In a multirate model, the timing controller entity generates the required rates from a single master clock using one or more counters and multiple clock enables.

The timing controller name derives from the name of the subsystem that is selected for code generation (the DUT), and the current value of the property TimingControllerPostfix. For example, if the name of your DUT is my_test, in the default case the coder adds the TimingControllerPostfix _tc to form the timing controller name my_test_tc.

Command-Line Information

Property: OptimizeTimingController

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Timing controller architecture

Specify whether to generate a reset for the timing controller.

Settings

Default: default

resettable: Generate a reset for the timing controller. If you select this option, the Clock inputs value must be Single.
default: Do not generate a reset for the timing controller.