Using Trigger Signals and Scalarization and Test Point DUT Port Generation Parameters

These parameters reside in the HDL Code Generation > Global Settings > Ports tab in the Configuration Parameters dialog box.

Use trigger signal as clock

This setting is a parameter in the HDL Code Generation > Global Settings > Ports tab in the Configuration Parameters dialog box.

Settings

Default: Off

On: For triggered subsystems, use the trigger input signal as a clock in the generated HDL code. Make sure that the Clock edge setting in the Configuration Parameters dialog box matches the Trigger type of the Trigger block inside the triggered subsystem.
Off: For triggered subsystems, do not use the trigger input signal as a clock in the generated HDL code.

Command-Line Information

Property: TriggerAsClock

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to generate HDL code that uses the trigger signal as clock for triggered subsystems within the sfir_fixed/symmetric_fir DUT subsystem, use either of these methods:

Pass the property as an argument to the makehdl function.

makehdl ('sfir_fixed/symmetric_sfir','TriggerAsClock','on')

When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.
```
hdlset_param('sfir_fixed','TriggerAsClock','on')
makehdl('sfir_fixed/symmetric_fir')
```

Enable HDL DUT port generation for tunable parameters

Disable this setting to prevent creation of DUT input ports for tunable parameters in the generated HDL code.

Settings

Default: On

On: The code generator creates DUT input ports for the tunable parameters signals in the generated HDL code.
Off: The code generator preserves the tunable parameters and does not create DUT input ports in the generated HDL code. Selecting off might speed up code generation.

Command-Line Information

Property: GenDUTPortForTunableParam

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as tunable parameters for the sfir_fixed/symmetric_fir DUT subsystem, to generate DUT input ports in the HDL code, use either of these methods:

Pass the property as an argument to the makehdl function.

makehdl ('sfir_fixed/symmetric_sfir','GenDUTPortForTunableParam','on')

When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.
```
hdlset_param('sfir_fixed','GenDUTPortForTunableParam','on')
makehdl('sfir_fixed/symmetric_fir')
```

Enable HDL DUT port generation for test points

Enable this setting to create DUT output ports for the test point signals in the generated HDL code.

Settings

Default: Off

On: When you enable this setting, the code generator creates DUT output ports for the test point signals in the generated HDL code. You can observe the test point signals and debug your design by connecting a Scope block to the output ports corresponding to these signals.
Off: When you disable this setting, the code generator preserves the test point signals and does not create DUT output ports in the generated HDL code.

Note

When you designate test points for states inside a Stateflow^® Chart, the code generator ignores this setting.

Command-Line Information

Property: EnableTestpoints

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as testpoints for the sfir_fixed/symmetric_fir DUT subsystem, to generate DUT output ports in the HDL code, use either of these methods:

Pass the property as an argument to the makehdl function.

makehdl ('sfir_fixed/symmetric_sfir','EnableTestpoints','on')

When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.
```
hdlset_param('sfir_fixed','EnableTestpoints','on')
makehdl('sfir_fixed/symmetric_fir')
```

Scalarize ports

Flatten vector ports into a structure of scalar ports in VHDL^® code.

Settings

Default: Off

On: When generating code for a vector port, generate a structure of scalar ports.
Off: When generating code for a vector port, generate a type definition and port declaration for the vector port.
dutlevel: When generating code for a vector port, generate a structure of scalar ports for vector ports that are at only DUT level. The DUT subsystem does not have to be at the top level of your model.

Dependency

When the target language (specified by the Language option) is VHDL, this option is enabled.

Command-Line Information

Property: ScalarizePorts

Type: character vector

Value: 'on' | 'off' | 'dutlevel'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.