Supported EDA Tools and Hardware
Intel Quartus Prime
Use this support package with these recommended versions:
Intel® Quartus® Prime Standard 21.1
Intel Quartus Prime Pro 22.4 (supported for Intel Arria® 10, Cyclone® 10 GX, and Intel Agilex® 7 only)
Intel Quartus II 13.1 (supported for Intel Cyclone III boards only)
For tool setup instructions, see Set Up FPGA Design Software Tools.
You can run FPGA-in-the-loop, FPGA data capture, or AXI manager over a JTAG cable to your board. However, each feature requires exclusive use of the JTAG cable, so you cannot run more than one feature at the same time. To allow other tools access to the JTAG cable, such as programming the FPGA, and Quartus SignalTap, you must discontinue the JTAG connection in MATLAB®. To release the JTAG cable:
FPGA-in-the-loop — Close the Simulink® model, or call the
releasemethod of the System object™.
FPGA data capture — Close the FPGA Data Capture app, release the System object, or close the Simulink model.
AXI manager — Call the
releasemethod of the object.
However, the nonblocking capture mode enables you to simultaneously use FPGA data capture and AXI manager, which share a common JTAG interface. For more information, see the "Simultaneous Use of FPGA Data Capture and AXI Manager" section of JTAG Considerations.
For Intel boards, the JTAG clock frequency is 12 or 24 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.
You can run FPGA-in-the-loop over an Ethernet connection.
There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.
FPGA-in-the-loop over a PCI Express® connection is supported only for 64-bit Windows operating systems.
Altera® Quartus II 15.0