This example shows how to implement an LTE transmitter design, including PSS, SSS, CRS, and MIB, optimized for HDL code generation.
The model in this example generates the baseband waveform specified by LTE standard TS 36.211. The waveform includes the primary synchronization signal (PSS), secondary synchronization signal (SSS), cell-specific reference signals (CRS), and the master information block (MIB) for transmission through the physical broadcast channel (PBCH). The model supports dynamic change of NCellID and NDLRB. The transmitter design is optimized for HDL code generation and, when implemented on an FPGA, can be used to transmit signals in real time over the air.
The architecture presented in this example is extensible and allows for integration of additional physical transmission channels such as physical downlink control channel (PDCCH), physical downlink shared channel (PDSCH), physical control format indicator channel (PCFICH), and physical HARQ indicator channel (PHICH).
The LTE HDL Transmitter architecture with PSS, SSS, CRS, and PBCH transmission chains is shown in the figure.
The input sampling rate is assumed to be at 10.24 Msps. PSS, SSS, PBCH, and CRS signals are generated in parallel, based on the input configuration. The LTE memory bank is sized to store one subframe of LTE data samples. The generated signals are written into memory corresponding to indices generated from the output ready signal of LTE OFDM Modulator. Then, the data is read out of LTE memory bank and modulated. The OFDM Modulator block uses a 2048-point FFT to support all NDLRBs. This architecture is designed to be extensible and scalable so that additional physical channels can be inserted as needed.
In this example, the transmitter transmits LTE signals for the following configurations:
Property Value ________________ __________________ Duplex mode FDD CellRefP 1 Bandwidth 1.4 - 20 MHz Cyclic prefix Normal/Extended Initial subframe 0 Initial frame 0 Ng Sixth/Half/One/Two PHICH duration Normal/Extended
The top level structure of ltehdlTransmitter model is shown below. HDL code can be generated for the HDL LTE Transmitter subsystem.
Input start is a pulse signal to trigger the transmission. You can configure other parameters, including NDLRB, NCellID, Cyclic prefix, Ng, and PHICH duration by modifying the
ltehdlTransmitter_init.m script. The
ltehdlTransmitter_init.m script is executed automatically by the model's
InitFcn callback. This script configures the individual blocks in the HDL LTE Transmitter subsystem. The input MIB bits are generated at a sampling rate of 10.24 Msps. The default initialization sets the transmitter to use these parameters:
enb.NDLRB = 6;
enb.CyclicPrefix = 'Normal';
enb.Ng = 'Sixth';
enb.PHICHDuration = 'Normal';
tx_cellids = [385 98 8 312 445 125];
The structure of the HDL LTE Transmitter subsystem is shown below. The Frame Controller controls the subframe and frame indices. The Input Sampler samples the inputs NDLRB and NCellID and then propagates the values to the subsequent blocks. The PSS & SSS generation generates PSS, SSS, and the corresponding memory address based on NDLRB and subframe index. The BCH Encoder and PBCH Encoder generate information for PBCH channel and memory addresses based on inputs. The CellRS Chain generates cell-specific reference signals and corresponding addresses. The Read Write Logic writes and reads the grid data from LTE Memory Bank and provides the data to LTE OFDM Modulator. The Discrete FIR Filter HDL Optimized filters modulated data using coefficients calculated based on the input configuration.
The Frame Controller subsystem assumes an input sampling rate of 10.24 Msps. It controls the subframe and radio frame boundaries by providing cellEnb signal to sample NCellID. It returns radio frame and subframe indices. It also provides syncStart, bchStart, and cellRSStart trigger signals to control the downstream blocks.
PSS & SSS Generation
The PSS & SSS chain generates the primary synchronization signal (PSS), secondary synchronization signal (SSS), and respective write addresses for LTE Memory Bank based on inputs NDLRB and NCellID. syncStart triggers the generation of PSS and SSS. The PSS and SSS occupy the same central 62 subcarriers of two OFDM symbols in a resource grid [ 1 ]. This subsystem generates two signals and their corresponding addresses at the same time, so both PSS and SSS can be written to LTE Memory Bank simultaneously.
The PSS sequence is generated from a frequency-domain Zadoff-Chu sequence [ 1 ], where the Zadoff-Chu root sequence index depends on NCellID2, which is derived from NCellID. There are three possible NCellID2 values, so all possible PSS sequences are precalculated and stored in
PSS_generation: Determines NCellID2 and reads the corresponding PSS sequence out of
PSS_indices: Computes the memory addresses required to write PSS data into LTE Memory Bank. This subsystem is equivalent to the LTE Toolbox™ function
The SSS sequence is an interleaved concatenation of two length-31 binary sequences. The concatenated sequence is scrambled with a scrambling sequence given by PSS. The combination of these sequences differs between subframe 0 and subframe 5[ 1 ]. The indices m0 and m1 are derived from physical-layer cell identity group, NCellID1[ 1 ]. These indices, and the sequences s(n), c(n), and z(n), are calculated and stored in
SSS_generation: Computes m0 and m1 based on NCellID and calculates indices required for sequences s(n), c(n), and z(n) based on subframe index. Generates SSS sequence as specified in [ 1 ].
SSS_indices: Computes the memory addresses required to write SSS data into LTE Memory Bank. This subsystem is equivalent to the LTE Toolbox™ function
Broadcast Channel (BCH) processes the MIB information arriving to the block in the form of a maximum of one transport block for every transmission time interval (TTI) of 40 ms. The block implements the following coding steps.
CRC Encoding: The entire transport block is used to calculate the CRC parity bits for a polynomial specified in [ 2 ]. The parity bits are then appended to the transport block. After appending, CRC bits are scrambled according to the transmit configuration. The CRC Encoder block is used with CRC mask set to 0.
Channel Coding: Input bits are tail-biting convolutionally encoded with an encoder of constraint length 7, and polynomial in octal. The % Convolutional Encoder block encodes the information bits. Because the coding rate of the encoder is 1/3, coded bits are then serialized using a Serializer1D block and control signals are resampled to 30.72 MHz (3 * 10.24 MHz).
Rate Matching: Coded bits are interleaved, followed by selection of bits for a particular length using an interleaved address [ 2 ]. For broadcast channel, because the length of the MIB is constant, interleaved write and read addresses are precalculated and stored in
rd_addrLUT respectively. Once all serialized coded bits have been written into interleaved addresses of RAM, the bits are read back using interleaved read addresses.
The physical broadcast channel processes the coded bits in the following steps.
Scrambling: Coded bits from BCH Encoder are scrambled with a cell-specific sequence using a Gold Sequence Generator block. The sequence is initialized with NCellID in each radio frame() fulfilling . The generated cell-specific sequence is scrambled with the input coded bits.
Memory: Complex modulated symbols corresponding to the physical broadcast channel for the initial radio frame are stored in
PBCH_RAM. For four consecutive radio frames, the number of bits to be transmitted on the physical broadcast channel is 1920 for normal cyclic prefix and 1728 for extended cyclic prefix. The Read Write Controller controls read and write addresses based on , since the periodicity of the broadcast channel (BCH) is 40 ms.
PBCH Indexing: Computes the memory addresses required to write PBCH data into LTE Memory Bank. The PBCH_indices subsystem is equivalent to the LTE Toolbox™ function
The cell-specific reference sequence is complex modulated values of a pseudo-random sequence as defined in [ 1 ]. The pseudo-random sequence generator is initialized with at the start of each OFDM symbol,as specified in [ 1 ].
CellRS_generation: Input cellRSStart triggers the generation of CRS signals. Since the CRS is available in four OFDM symbols of a single subframe, this subsystem calculates a 4-element vector for every subframe. The Gold Sequence Generator block is initialized with vector to represent multiple channels and provides four different cell-specific pseudo-random sequences. The Write Controller controls writing of these sequences into four memory banks in
CellRS_RAM. It also returns rd_en, which enables reading data out of
CellRS_RAM. The Read Controller controls reading of CRS data corresponding to four OFDM symbols, and returns rd_bank and rd_valid to select an appropriate sequence. The sequence is then mapped to complex QPSK modulated symbols.
CellRS_indices: Computes the addresses required to write CRS data into LTE Memory Bank. This subsystem is equivalent to the LTE Toolbox™ function
Read Write Logic
The Read Write Logic subsystem contains a Write Selector, Read Selector, LTE Memory Bank and a Grid Bank Select. The LTE Memory Bank storage capacity is one subframe of complex modulated symbols at the largest supported LTE bandwidth (20 MHz).
The Write Selector is responsible for writing subframes of data into the memory banks. As mentioned in the PSS & SSS generation section, PSS and SSS occupy central subcarriers. The Write Selector first writes PSS and SSS simultaneously into corresponding locations in LTE Memory Bank. Then, it writes PBCH data, followed by CRS data, and then returns rd_enb to indicate the write is complete. The LTE Memory Bank can store 14 x 2048 x 16-bit complex values, that is, 14 OFDM symbols, each containing 2048 complex values.
The Read Selector reads the symbol from the LTE Memory Bank based on rd_enb and ready from the LTE OFDM Modulator block. The LTE Memory Bank returns the data from all 14 memory banks. The Grid Bank Select selects the appropriate symbols from the LTE Memory Bank to form the resource grid output.
Since the scope of this example is limited to PSS, SSS, CRS, and PBCH transmission, the LTE Memory Bank is erased at the start of every subframe, before writing new data into the memory.
OFDM Modulation and Filtering
Grid data from LTE Memory Bank is OFDM-modulated using the OFDM Modulator block with 'Output data sample rate' parameter set to 'Match output data sample rate to NDLRB'. The modulated data is filtered using a Discrete FIR Filter HDL Optimized block with coefficients generated at a sampling rate corresponding to the NDLRB.
After running the simulation, the
ltehdlTransmitter_PostSim.m script is executed automatically by the model's
StopFcn callback. The model displays three figures illustrating the outputs and results. The first plot illustrates the output of the filtered OFDM-modulated samples. The second and third plot display the cell search and MIB decoding results obtained by decoding the transmitted data using LTE Toolbox™ functions. These results verify the behavior of the transmitter design.
LTE Transmitted Waveform
The first subplot shows the Power Spectral Density (PSD) output of the filtered data. The result is compared with the PSD of the reference output signal that is generated using LTE Toolbox™. This comparison shows the equivalence of the two signals. For the figure shown, a transmission bandwidth of BW = 1.4MHz was used.
The second subplot shows the absolute-value of the transmitted waveform. The result is plotted on top of the same portion of the absolute-value of a reference transmitter signal that is generated using LTE Toolbox™. The plot also shows the difference between the HDL implementation and the reference signal. This comparison shows the minimal error between the two transmitted waveforms.
Cell Search & MIB Decoding Results
The following plots show the results of a cell search and MIB decoding simulation. It verifies the transmitter performance and compares the HDL transmitter implementation against the same LTE transmitter configuration using LTE Toolbox™ functions.
NCellID after Cell Search: Displays the LTE cell search results.
Cell-wide settings after MIB decoding: Displays the fields of MIB after MIB decoding - NDLRB, Ng, PHICH duration, and System Frame Number (SFN).
Validation with Cell Search and MIB Recovery Example
Performance of HDL LTE Transmitter can also be verified using the LTE HDL MIB Recovery example, by setting 'Output data sample rate' property of the OFDM Modulator block to 'Use maximum output data sample rate' and initializing the transmit filter with coefficients at the maximum sampling rate.
To check and generate HDL for this example, you must have an HDL Coder™ license. Use the
makehdltb commands to generate HDL code and HDL test bench for the HDL LTE Transmitter subsystem. Because the inputs in this example depend on
TotalSubframes, the test bench generation takes a long time.
The HDL LTE Transmitter subsystem was synthesized on a Xilinx® Zynq®-7000 ZC706 evaluation board. The post place and route resource utilization results are shown in the table below. The design met timing with a clock frequency of 207.5 MHz.
Resources Usage _______________ _____ Slice Registers 12436 Slice LUTs 13130 RAMB18 11 RAMB36 41 DSP48 47
3GPP TS 36.211 "Physical channels and modulation".
3GPP TS 36.212 "Multiplexing and channel coding".