Position Generator

Generate position ramp of fixed frequency

Since R2020a

• 

Libraries:
Motor Control Blockset / Controls / Control Reference
Motor Control Blockset HDL Support / Controls / Control Reference

Description

The Position Generator block generates a position ramp signal (with a frequency that is identical to that of the reference voltage signal) using the position increment value of the reference signal.

We recommend that you use fixed-step discrete solver for this block to enable code generation and ensure accurate simulation.

Examples

Sensorless Field-Oriented Control of PMSM

Implements the field-oriented control (FOC) technique to control the speed of a three-phase permanent magnet synchronous motor (PMSM). For details about FOC, see Field-Oriented Control (FOC).

Open Model

Run 3-Phase AC Motors in Open-Loop Control and Calibrate ADC Offset

Uses open-loop control (also known as scalar control or Volts/Hz control) to run a motor. This technique varies the stator voltage and frequency to control the rotor speed without using any feedback from the motor. You can use this technique to check the integrity of the hardware connections. A constant speed application of open-loop control uses a fixed-frequency motor power supply. An adjustable speed application of open-loop control needs a variable-frequency power supply to control the rotor speed. To ensure a constant stator magnetic flux, keep the supply voltage amplitude proportional to its frequency.

Open Model

Field-Oriented Control of Induction Motor Using Speed Sensor

Implements the field-oriented control (FOC) technique to control the speed of a three-phase AC induction motor (ACIM). The FOC algorithm requires rotor speed feedback, which is obtained in this example by using a quadrature encoder sensor. For details about FOC, see Field-Oriented Control (FOC).

Open Model

Field-Weakening Control (with MTPA) of PMSM

Implements the field-oriented control (FOC) technique to control the torque and speed of a three-phase permanent magnet synchronous motor (PMSM). The FOC algorithm requires rotor position feedback, which is obtained by a quadrature encoder sensor. For details about FOC, see Field-Oriented Control (FOC).

Open Model

Ports

Input

∆θ — Position increment value

scalar

Position increment value of a fixed frequency reference voltage signal (in either per unit, radians, or degrees). These equations describe how you can compute the position increment value:

• $$\Delta \theta \text{ (per unit) }=\text{ Frequency }\times \text{ Sample Time}$$

• $$\Delta \theta \text{ (radians) }=\text{ 2}\pi \times \text{ Frequency }\times \text{ Sample Time}$$

• $$\Delta \theta \text{ (degrees) }=\text{ 360}\times \text{ Frequency }\times \text{ Sample Time}$$

Note

If the preceding Δθ computation causes a precision loss in the block input, the block might not replicate the actual Frequency accurately.

Data Types: single | double | fixed point

Reset — External reset signal

scalar

External pulse that resets the position ramp output based on the value of the External reset parameter.

Dependencies

To enable this port, set External reset to either active high resets to zero or active high resets to initial condition.

Data Types: single | double | fixed point

Output

θ_e — Reference voltage position

scalar

Position or phase value of the reference voltage signal (in either per unit, radians, or degrees).

Data Types: single | double | fixed point

Parameters

Theta Units — Unit of θ

Per-unit (default) | Radians | Degrees

Unit of the input position increment value and the output reference voltage position.

Initial theta output — Initial value of θe

0 (default) | scalar

Output position ramp value (in either per unit, radians, or degrees) at initial time (0 seconds).

External reset — Output value on reset

none (default) | active high resets to zero | active high resets to initial condition

Output position ramp value (in either per unit, radians, or degrees) at the time when the block receives an active high external reset pulse. You can reset the output to either zero or to equal the value of the Initial theta output parameter.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restriction

The block supports HDL code generation only when you set the External reset parameter to none.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2020a