How an audio beamforming system simulation model in Simulink® can have improved performance using dataflow domain. It uses the dataflow domain in Simulink® to automatically partition the data-driven portions of the communications system into multiple threads and thereby improving the performance of the simulation by executing it on your desktop's multiple cores.

Simulates a monostatic radar system. It uses dataflow domain in Simulink® to automatically partition the data-driven portions of the radar system into multiple threads and thereby improving the performance of the simulation by executing it on your desktop's multiple cores.

Phased Array System Toolbox™ can be used to model an end-to-end phased array system - generate a transmitted waveform, simulate the target return, and then process the received signal to detect the target. This is shown in the examples: Simulating Test Signals for a Radar Receiver and Waveform Design to Improve Range Performance of an Existing System. This example shows how to simulate such a system in streaming mode so you can run the simulation for a long time and observe the system dynamics.

This tutorial is the first of a two-part series that will guide you through how to develop a beamformer in Simulink® suitable for implementation on hardware, such as a Field Programmable Gate Array (FPGA). It will also show how to compare the results of the implementation model with those of a behavioral model. The second part of the tutorial FPGA Based Beamforming in Simulink: Part 2 - Code Generation shows how to generate HDL code from the implementation model and verify that the generated HDL code produces the correct results compared to the behavioral model.

This tutorial is the second of a two-part series that will guide you through the steps to generate HDL code for a beamforming algorithm and verify that the generated code is functionally correct. The first part of the tutorial FPGA Based Beamforming in Simulink: Part 1 - Algorithm Design shows how to develop an algorithm in Simulink suitable for implementation on hardware, such as a Field Programmable Gate Array (FPGA), and how to compare the output of the fixed-point, implementation model to that of the corresponding floating-point, behavioral model.