Simulink Design Verifier Options
Options in Configuration Parameters Dialog Box
You can set options for Simulink® Design Verifier™ analysis in the Configuration Parameters dialog box. To view the options, open Design Verifier tab. In the Prepare section, from the drop-down menu for the mode settings, and click Settings. The Design Verifier pane of the model configuration parameters opens.
By default, options for Simulink Design Verifier do not appear in the Configuration Parameters dialog box. When you open the Design Verifier tab, Simulink Design Verifier associates its default options with the model. After you save the model, you can access options for Simulink Design Verifier directly from the Configuration Parameters dialog box.
See Set Model Configuration Parameters for a Model for more information about working with this interface.
Design Verification Options Objects
You can use the sldvoptions
function
to specify Simulink
Design Verifier options at the command line.
To view in the MATLAB® Command Window the design verification options associated with a Simulink model, use the following syntax:
opts = sldvoptions('model_name'); get(opts)
Command-Line Parameters for Design Verification Options
Use the following parameters to configure the behavior of Simulink
Design Verifier.
Use the get_param
and set_param
functions to retrieve and
specify values for these parameters programmatically.
For each parameter, the Location column indicates where you can set its value in the Configuration Parameters dialog box. The Values column shows the type of value required, the possible values (separated with a vertical line), and the default value (enclosed in braces).
Parameter | Location | Values |
---|---|---|
| Set by the Floating point absolute tolerance parameter on the Design Verifier > Test Generation pane. | double |
| Set by the Assertion blocks parameter on the Design Verifier > Property Proving pane. |
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| Set by the Automatic stubbing of unsupported blocks and functions parameter on the Design Verifier pane. |
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| Set by the Apply block replacements parameter on the Design Verifier > Block Replacements pane. |
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| Set by the File path of the output model parameter on the Design Verifier > Block Replacements pane. | character array |
| Set by the List of block replacement rules parameter on the Design Verifier > Block Replacements pane. | character array |
| Set by the Additional options for code analysis parameter on the Design Verifier pane. | character array
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| Set by the Coverage data file parameter on the Design Verifier > Test Generation pane. | character array |
| Set by the Ignore objectives based on filter parameter on the Design Verifier pane. |
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| Set by the Filter file(s) parameter on the Design Verifier pane. | character array |
| Set by the Data file name parameter on the Design Verifier > Results pane. | character array |
| Set by the Coverage objectives to be analyzed parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Specified minimum and maximum value violations parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Use specified input minimum and maximum values parameter on the Design Verifier pane. |
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| Set by Run exhaustive analysis on the Design Verifier > Design Error Detection pane. |
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| Set by Specified block input range violations on the Design Verifier > Design Error Detection pane. |
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| Set by Dead logic (partial) on the Design Verifier > Design Error Detection pane. |
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| Set by the Division by zero parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Data store access violations parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Non-finite and NaN floating-point values parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Integer overflow parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Out of bound array access parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Subnormal floating-point values parameter on the Design Verifier > Design Error Detection pane. |
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| Set by the Display report parameter on the Design Verifier > Report pane. |
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| Set by the Extend existing test cases parameter on the Design Verifier > Test Generation pane. |
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| Set by the Data file parameter on the Design Verifier > Test Generation pane. | character array |
| Set by the Harness model file name parameter on the Design Verifier > Results pane. | character array |
| Set by the Harness source parameter on the Design Verifier > Results pane. |
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| Set by the Ignore objectives satisfied in existing coverage data parameter on the Design Verifier > Test Generation pane. |
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| Set by the Ignore objectives satisfied by existing test cases parameter on the Design Verifier > Test Generation pane. |
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| Set by the Include relational boundary objectives parameter on the Design Verifier > Test Generation pane. |
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| Set by the Make output file names unique by adding a suffix check box on the Design Verifier pane. |
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| Set by the Maximum analysis time parameter on the Design Verifier pane. | double |
| Set by the Maximum test case steps parameter on the Design Verifier > Test Generation pane. | int32 |
| Set by the Maximum violation steps parameter on the Design Verifier > Property Proving pane. | int32 |
| Set by the Mode parameter on the Design Verifier pane. |
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| Set by the Model coverage objectives parameter on the Design Verifier > Test Generation pane. |
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| Set by the Reference input model in generated harness parameter on the Design Verifier > Results pane of the Configuration Parameters dialog box. |
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| Set by Output folder on the Design Verifier pane. | character array |
| Set by Constraint column in Parameter Table on the Design Verifier > Parameters pane. | double array |
| Set by Name column in Parameter Table on the Design Verifier > Parameters pane. | double array |
| Set by Use column in Parameter Table on the Design Verifier > Parameters pane. | cell array |
| Set by Enable parameter configuration on the Design Verifier > Parameters pane. |
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| Set by Parameter configuration file on the Design Verifier > Parameters pane. This parameter is disabled when | character array |
| Set by Use parameter table on the Design Verifier > Parameters pane. When set to |
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| Set by the Proof assumptions parameter on the Design Verifier > Property Proving pane. |
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| Set by the Strategy parameter on the Design Verifier > Property Proving pane. |
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| Set by the Randomize data that do not affect the outcome parameter on the Design Verifier > Results pane. |
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| Set by the Rebuild model representation parameter on the Design Verifier pane. |
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| Set by the Run additional analysis to reduce instances of rational approximation parameter on the Design Verifier pane. |
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| Set by the Floating point relative tolerance parameter on the Design Verifier > Test Generation pane. | double |
| Set by the Report file name parameter on the Design Verifier > Report pane. | character array |
| Set by the Include screen shots of properties parameter on the Design Verifier > Report pane. |
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| Set by the Generate additional report in PDF format parameter on the Design Verifier > Report pane. |
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| Set by the Include expected output values parameter on the Design Verifier > Results pane. |
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| Set by the Generate separate harness model after analysis parameter on the Design Verifier > Results pane. |
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| Set by the Generate report of the results parameter on the Design Verifier > Report pane. |
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| Set by the Support S-Functions in the analysis parameter on the Design Verifier pane. |
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| Set by the Test Harness Name parameter on the Design Verifier > Results pane. | character array |
| Set by the Test File Name parameter on the Design Verifier > Results pane. | character array |
| Set by the Use strict propagation conditions parameter on the Design Verifier > Test Generation pane. |
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| Set by the Test conditions parameter on the Design Verifier > Test Generation pane. |
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| Set by the Test generation target parameter on the Design Verifier > Test Generation pane. |
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| Set by the Test objectives parameter on the Design Verifier > Test Generation pane. |
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| Set by the Test suite optimization parameter on the Design Verifier > Test Generation pane. If you analyze
your model by using the |
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| Set by the Validate test cases or counterexamples with parallel computing parameter on the Design Verifier pane. |
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