This example shows how to design a temporal logic scheduler in Stateflow®. The temporal logic scheduler design pattern allows you to schedule Simulink® subsystems to execute at specified times. Stateflow schedulers extend control of subsystem execution in a Simulink model, which determines order of execution implicitly based on block connectivity and sample time propagation.
In this example, the Temporal Logic Scheduler chart contains two states that schedule the execution of three function-call subsystems (A1, A2, and A3) at different rates, as determined by the temporal logic operator
FastScheduler state is active, the chart schedules function calls to different Simulink subsystems at a fraction of the base rate at which the input event
call wakes up the chart.
The chart sends an event to execute subsystem A1 at the base rate.
The chart sends an event to execute subsystem A2 at half the base rate.
The chart sends an event to execute subsystem A3 at one quarter the base rate.
SlowScheduler state is active, the chart schedules function calls for A1, A2, and A3 at 1/8, 1/16, and 1/32 times the base rate.
The chart switches between the fast and slow execution modes after every 100 invocations of the
When you simulate the model, the scope displays the value of y at each time step.
The changes in value illustrate the different rates of execution.
When the chart executes the subsystems at a slow rate (for example, from to , from to , and from to ), the values change slowly.
When the chart executes the subsystems at a fast rate (for example, from to and from to ), the values change rapidly.