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Access AXI slave memory on FPGA board from MATLAB®

Access on-board memory locations from MATLAB, using the MATLAB AXI master IP in your FPGA design, and the aximaster object. The object connects to the IP over the JTAG cable, and allows read and write commands to slave memory locations from the MATLAB command line.


setupAXIMasterForQuartus Add AXI master IP path to Quartus project
readmemoryRead data out of AXI4 memory-mapped slaves
writememoryWrite data to AXI4 memory-mapped slaves
releaseRelease JTAG cable resource


aximaster Read and write memory locations on an FPGA board from MATLAB


Set Up for MATLAB AXI Master

High-level steps for accessing memory on an FPGA board from MATLAB

Ethernet MATLAB as AXI Master

Integrate and configure Ethernet MATLAB as AXI Master using User Datagram Protocol (UDP).

PCI Express MATLAB as AXI Master

Integrate and configure of MATLAB as AXI Master IP over PCI Express.

Featured Examples