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Design Considerations for Data Capture

Signals to Capture

To get started with FPGA data capture, you must specify port names and sizes for the generated IP. You then connect these ports to the signals in your design that you want to capture. You can specify bit widths between 1 and 128 bits. The default data type of the captured data depends on this bit width.

The FPGA data capture tools do not limit the total number of signals or bits you can capture. You are limited only by the hardware resource usage on your FPGA. When you select signals and the depth of the capture buffer, consider the memory and signal routing resources required on the FPGA.

In the FPGA Data Capture Component Generator, you can specify a signal for use as data or trigger. When you specify a signal as data, the signal is captured to the sample buffer and returned to MATLAB®, but it cannot contribute to a trigger condition. A data signal uses memory resources on the FPGA. When you specify a signal as a trigger, it is available for defining a trigger condition at capture time, but is not captured and returned to MATLAB. A trigger signal uses logic resources on the FPGA. You can also specify that the signal is used as both trigger and data.

At capture time, you can configure the data type of the variable returned to MATLAB or Simulink®. You can select built-in types, or, with Fixed-Point Designer™, you can specify fixed-point data types. If you do not have Fixed-Point Designer, data capture can only return built-in data types, such as uint8. In this case, you must specify ports for the generated IP that match the sizes of the built-in data types, that is, 1, 8, 16, 32, or 64 bits.

Capture Timing

The data capture feature captures a fixed-size buffer of data each time you request a capture. The feature does not stream continuous data from your FPGA into MATLAB or Simulink. You can capture a buffer immediately, or you can configure a logical trigger condition to control when the buffer is captured. You can also configure the timing of the capture relative to the cycle the trigger is detected in, and configure the capturing of multiple windows of trigger events. While the data capture IP waits for a trigger, captures data, and returns the captured data to MATLAB, you cannot initiate a new capture request. Therefore, you cannot capture back-to-back buffers from the FPGA.

Use this feature to investigate design behavior around a specific event or to sample data occasionally, rather than for continuous observation. For more information about how to use trigger conditions, see Triggers.

JTAG Considerations

The generated data capture IP can coexist in your design with other IPs that use the JTAG connection, such as MATLAB AXI master, Altera® SignalTap II or Xilinx® Vivado® Logic Analyzer cores. However, only one of these applications can use the JTAG cable at a time. You must close the FPGA Data Capture app or model, or release the object, to return the JTAG resource for use by other applications.

The most common conflicting use of the JTAG cable is to reprogram the FPGA. You must stop any FPGA data capture or MATLAB AXI master JTAG connection before you can use the cable to program the FPGA.

The maximum data rate between host computer and FPGA is limited by the JTAG clock frequency. For Intel® boards, the JTAG clock frequency is 12 or 24 MHz. For Xilinx boards, the JTAG clock frequency is 33 or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.

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