This is machine translation

Translated by Microsoft
Mouseover text to see original. Click the button below to return to the English version of the page.

Note: This page has been translated by MathWorks. Click here to see
To view all translated materials including this page, select Country from the country navigator on the bottom of this page.


System object: hdlverifier.FPGADataReader
Package: hdlverifier

Configure operator that combines individual signal value comparisons into overall trigger condition




setTriggerCombinationOperator(DC,operator) specifies the logical operator that combines comparisons of individual signals into an overall trigger condition.

Input Arguments

expand all

This object is the customized object you created using the FPGA Data Capture Component Generator app.

The trigger condition can be composed of value comparisons of one or more signals. Combine these value comparisons with only one type of logical operator. Suppose three signals, A, B, and C, make up the trigger condition. The options are:

A == 10 AND B == 'Falling edge' AND C = 0

A == 10 OR B == 'Falling edge' OR C = 0
You cannot mix and match the combination operators. See Triggers.