System object: hdlverifier.FPGADataReader
Package: hdlverifier

Configure operator that combines individual signal value comparisons into overall trigger condition




setTriggerCombinationOperator(DC,operator) specifies the logical operator that combines comparisons of individual signals into an overall trigger condition.

Input Arguments

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Customized data capture object created using the FPGA Data Capture Component Generator app.

The trigger condition can be composed of value comparisons of one or more signals. Combine these value comparisons with only one type of logical operator. Suppose three signals, A, B, and C, make up the trigger condition. The options are:

A == 10 AND B == 'Falling edge' AND C = 0

A == 10 OR B == 'Falling edge' OR C = 0
You cannot mix and match the combination operators. See Triggers.