System object: hdlverifier.FPGADataReader
Capture one buffer of data from HDL IP core running on FPGA
dataOut = step(DC)
Alternatively, instead of using the
to perform the operation defined by the System
object™, you can
call the object with arguments, as if it were a function. For example,
= step(obj,x) and
y = obj(x) perform
live signal data from a design running on an FPGA. The FPGA must contain an HDL IP core
generated from the FPGA Data
Capture Component Generator app.
dataOut = step(
dataOut is a structure
that contains a field for each signal captured. Call
specify the data type of each captured signal.
If at least one signal is enabled as part of the trigger condition,
the HDL IP core waits for a match of the trigger condition and then
captures the data. If no signals are enabled as part of the trigger
condition, the HDL IP core captures and returns the buffered data
immediately. When you create the object, no trigger condition is set
by default. Call
configure a trigger condition.
dataOut— Captured data
Structure containing a vector of Sample depth values for each signal requested for data capture at generation time. The fields of the structure have the names you specified for the signals.