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System object: hdlverifier.FPGADataReader
Package: hdlverifier

Capture one buffer of data from HDL IP core running on FPGA


dataOut = step(DC)



Alternatively, instead of using the step method to perform the operation defined by the System object™, you can call the object with arguments, as if it were a function. For example, y = step(obj,x) and y = obj(x) perform equivalent operations.

dataOut = step(DC) captures live signal data from a design running on an FPGA. The FPGA must contain an HDL IP core generated from the FPGA Data Capture Component Generator app. dataOut is a structure that contains a field for each signal captured. Call setDataType to specify the data type of each captured signal.

If at least one signal is enabled as part of the trigger condition, the HDL IP core waits for a match of the trigger condition and then captures the data. If no signals are enabled as part of the trigger condition, the HDL IP core captures and returns the buffered data immediately. When you create the object, no trigger condition is set by default. Call setTriggerCondition and setTriggerCombinationOperator to configure a trigger condition.

Input Arguments

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This object is the customized object you created using the FPGA Data Capture Component Generator app.

Output Arguments

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Structure containing a vector of Sample depth values for each signal requested for data capture at generation time. The fields of the structure have the names you specified for the signals.