A trigger condition is a logical statement that defines when to capture data from the FPGA. Use a trigger condition to capture data around an event of interest on the FPGA. Capture multiple occurrences of an event by setting Number of capture windows to the desired value. A trigger condition is composed of value comparison tests on one or more FPGA signals. For example:
counter == 100
All trigger comparisons are synchronous. When you specify an edge condition for a Boolean signal, the IP core compares the current sampled value with the sampled value from the previous clock cycle.
fifo_full == 'Rising edge'
The trigger condition is met when all terms of the condition are true on the same clock cycle. You can use only a single value comparison per signal.
receiver_state == 3 OR message_detected == 'High'
fifo_cnt == 0 AND fifo_pop == 'High'
You can use only a single type of logical operator in the trigger
condition. You cannot mix
receiver_state == 3 AND message_addr == 148 AND pkt_type == 5
fifo_empty == 'Rising edge' OR fifo_full == 'Rising edge' OR memctrl_state == 2
At generation time, specify which signals you want to be available for use in trigger conditions. A signal can be a trigger without capturing data, or it can be both a trigger and a captured signal. You can modify the trigger condition at capture time, using any signals you specified as triggers. The data capture IP core on the FPGA receives the trigger definition from MATLAB® and configures on-chip muxes to detect the event.
When you use the FPGA Data Capture app, or the FPGA Data Reader block, set the trigger condition on the Trigger tab. Each line in the table is the value comparison for one signal. To combine the signal values, use the Trigger combination operator. To show a signal on this tab, you must specify the signal as a trigger at generation time.
When you use the
object™, configure the trigger condition using the
methods. To check your configuration, call
If you do not enable a trigger condition on any signal, the data capture IP core captures data immediately.
You can change the relative position of the trigger detection cycle within the capture buffer. Use this feature to capture the relevant data, whether it is before or after the trigger event.
Suppose you want to debug the rates of pushes and pops to a
FIFO design. You can set a trigger on a
of the signals
By default, the clock cycle when the trigger is detected is
the first sample of the capture buffer. The IP core captures a buffer
starting from the cycle when
fifo_full goes high.
To debug the
fifo_full condition, observe the signals before the trigger
condition occurs. In the capture settings, change the Trigger position to
3/4 of the window depth using the tic mark on the slider. For example, if your Sample
depth is 128, and Number of capture windows is 1, then
window depth is 128. The trigger event is at sample 96 of that window. The
IP core captures a buffer that contains 96 samples before the trigger event, and 36 samples
after the trigger event. This setting captures data that shows the lead-up to the trigger event,
and the aftermath. The location of the trigger event is shown with the vertical cursor at
You can set the Trigger position to a number of samples between 0 and the window depth-1, inclusive. When you set the trigger position equal to window depth-1, the last sample corresponds to the cycle when the trigger occurs.
To observe more than one occurrence of the trigger event, change the Number of capture windows to the desired number.
The following example has Number of capture windows set to 4,
Sample depth to 128, and Trigger position set to 0.
This will capture four windows, each window depth is 32 samples, starting
fifo_full goes high: