Write data to IP core on the target hardware through AXI4-Lite interface
Embedded Coder Support Package for Intel SoC Devices
Use the AXI4 interface to write vector data from the embedded processor to a contiguous group of registers on the Programmable Logic IP Core. The AXI4 Write block only supports the AXI4-Lite protocol, allowing for simple, low-throughput memory-mapped communication. Typical uses for this protocol include writing to control and status registers.
The sample rate of the block input signal controls how often this block writes data to the register.
Port_1 — Input signal
The 1-D vector written to the registers on the IP core starting at
Offset address from the base address of the IP core.
Device name — Path and file name of IP core device
Enter the path and file name of the IP core device.
If you are using HDL Coder™ to generate the IP core, the IP core is mapped to
Offset address — Offset from the base address of the IP core to the register
hex2dec( '0100' ) (default)
Enter the offset from the base address of the IP core to the register. The block
reads data from this register. Use the
hex2dec function when you specify the offset address using a hexadecimal
number expressed as a character vector.
Introduced in R2014b
Custom IP Report (HDL Coder)
- Intel SoC Devices (HDL Coder)
- Hardware-Software Co-Design Workflow for SoC Platforms (HDL Coder)
- Default System Reference Design (HDL Coder Support Package for Intel SoC Devices)