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Default System with External DDR4 Memory Access Reference Design

With the HDL Coder™ software, you can generate an HDL IP core with AXI4 Master interfaces. If you specify Altera Arria10 SoC development kit as the Target platform, you can integrate the HDL IP core into the Default System with External DDR4 Memory Access reference design. To use this reference design, you must have HDL Verifier™ installed. This figure shows a high-level block diagram of the Default System with External DDR4 Memory Access reference design architecture.

In this architecture, the HDL DUT IP block corresponds to the IP core that is generated from the IP Core Generation workflow. Other blocks in the architecture represent the predefined reference design, which consists of a MATLAB® based JTAG AXI Master IP that is provided by HDL Verifier. After you run the FPGA design on the board, by using the JTAG AXI Master IP, you can use the input data in MATLAB to initialize the onboard DDR4 external memory. The HDL DUT IP core reads the input data from the external memory through the AXI4 Master interface. The IP core then performs the algorithm computation and writes the result to DDR4 memory through the AXI4 Master interface. The JTAG AXI Master IP can read the result from DDR4 memory, and then verify the result in MATLAB.

Specifications

  • The reference design supports either AXI4 Master Read channel or AXI4 Master Write channel, or both AXI4 Master Read and AXI4 Master Write channels.

  • AXI4 Master Maximum Data bitwidth: 128-bit

  • AXI4 Master Address bitwidth: 32-bit

For the DUT IP core AXI4 Master interface:

  • DDR4 external memory address range: x00000000 to x7FFFFFFF

  • Default AXI4 Master Read channel base address: x00000000

  • Default AXI4 Master Write channel base address: x00000000

For the MATLAB AXI Master interface:

  • DDR4 external memory address range: x00000000 to x7FFFFFFF

  • DUT IP core base address: x80000000

Targeting the Reference Design

To target your algorithm in Simulink® to the Default System with External DDR4 Memory Access reference design:

  1. Model your algorithm with the simplified AXI4 Master protocol. To generate an IP core with AXI4 Master interfaces, in your DUT interface, implement the Data signals and AXI4 Master Read and AXI4 Master Write controls signals as a bus. For more information, see Model Design for AXI4 Master Interface Generation (HDL Coder).

  2. Open the HDL Workflow Advisor. In the Set Target Device and Synthesis Tool task, specify IP Core Generation as the Target workflow. For Target platform, select Altera Arria10 SoC development kit.

In the Set Target Reference Design task, HDL Coder sets Default System with External DDR4 Memory Access as the Reference design. Go through the workflow to generate the HDL IP core, and to integrate the IP core into the Default System with External DDR4 Memory Access reference design.

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