Support SPI Communication
SPI, or Serial Peripheral Interface, is a synchronous, full duplex serial communication protocol between high-speed devices over short distances. The SPI protocol supports a single controller with one or more peripherals. The controller can communicate to any peripheral on the bus, but each peripheral can communicate only with the controller.
The SPI Controller Transfer block in the support package library enables communication with other SPI devices. You can use this block only when you use your hardware as the controller device.
With SPI, you can:
Connect various sensors to boards to measure different quantities such as temperature, pressure.
Connect various shields to boards to enhance capabilities such as WiFi shield.
Access an SD card to store data or extend the available memory.
You can set SPI properties such as the SPI clock out frequency (in MHz), SPI mode, and the Bit order in the Configuration Parameters > Hardware Implementation > SPI properties section.
SPI uses a four-wire serial bus for communication: MISO, MOSI, SCK, and SS. The MISO, MOSI, and the SCK lines are common to all devices. The SS line is specific to each peripheral.
CIPO (Controller In Peripheral Out) – This line is the peripheral line for sending data to the SPI controller.
COPI (Controller Out Peripheral In) – This line is the controller line for sending data to the SPI peripherals.
SCK (Serial Clock) –The controller generates the clock pulses that synchronize the data transmission.
PS (Peripheral Select) – This is specific to the device. This is the pin on each device that the SPI controller can use to enable and disable the device. This signal is an ‘active low’ signal which means a device becomes a peripheral when its SS pin is set to low.
The SPI lines over In Circuit Serial Programming (ICSP) header are consistent across all the boards shown as follows.
The SPI controller sets the clock with a frequency supported by the SPI peripheral with which the controller wants to communicate.
The controller selects the peripheral by setting the SS pin of peripheral to low (0). The controller can select only one peripheral at a time.
As each SPI transfer is a full duplex transmission, the controller sends a bit on MOSI line and the peripheral reads it. The peripheral also sends a bit on the MISO line and the controller reads it.
When the controller makes a data transfer, the peripheral cannot opt out of sending data. However, the peripheral device sends dummy bytes (usually all 1s or all 0s) when communication is one-way. Similarly, when the controller reads data from a peripheral, the peripheral knows to ignore the data that the controller sends.
When the transfer is complete, the controller stops toggling the SCK and mostly pulls up the SS to deselect the peripheral.
During the data transmission, the other peripherals on the SPI bus that have not been selected by the controller ignore the SCK and the MOSI signals, and do not drive the MISO.
SPI Transfer Modes
An SPI controller sets the clock polarity and the clock phase.
Clock Polarity (CPOL) – is the default value (HIGH/LOW) of SCK signal when the bus is idle.
CPOL = 0 means a default LOW value of SCK when bus is idle. CPOL = 1 means default HIGH value of SCK when bus is idle.
Clock Phase (CPHA) – indicates, if the clock data is sampled at LEADING (first) or TRAILING (second) edge of SCK.
CPHA = 0 means sample at LEADING edge of SCK and CPHA = 1 means sample at TRAILING edge of SCK, regardless of whether the clock edge is RISING or FALLING.
The combination of polarity and phase are referred to as SPI modes. The SPI modes 0–3 are shown in the table.
|Mode||Clock Polarity (CPOL)||Clock Phase (CPHA)|