MATLAB as AXI Master

Access AXI slave memory on FPGA board from MATLAB^®

Access on-board memory locations from MATLAB by using the MATLAB AXI Master IP in your FPGA design and the aximaster object. The object connects to the IP over a JTAG, Ethernet, or a PCIe interface and enables read and write commands to slave memory locations from the MATLAB command line.

Functions

`setupAXIMasterForVivado`	Add AXI master IP path to Vivado project
`readmemory`	Read data out of AXI4 memory-mapped slaves
`writememory`	Write data to AXI4 memory-mapped slaves
`release`	Release JTAG or Ethernet cable resource
`copyImageToHostSDCardPath`	Copy board-specific SD card image files to host SD card location
`loadImageToTargetSDCardPath`	Load board-specific SD card image files to target SoC device SD card location
`loadBitstream`	Load custom FPGA bitstream and its corresponding DTB file to target SoC device

Objects

aximaster Read and write memory locations on FPGA board from MATLAB

Blocks

AXI Master Read	Read memory locations on FPGA board from Simulink
AXI Master Write	Write memory locations on FPGA board from Simulink

Topics

Set Up MATLAB as AXI Master

High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink^®.

Ethernet MATLAB as AXI Master

Integrate and configure Ethernet MATLAB as AXI Master.

Ethernet MATLAB as AXI Master for Xilinx Zynq SoC Devices

Configure Ethernet MATLAB as AXI Master for Xilinx Zynq SoC devices.

PCI Express MATLAB as AXI Master

Integrate and configure MATLAB as AXI Master IP over PCI Express.

Use Simulink to Access FPGA Locations

Access memory-mapped locations on an FPGA board from Simulink.

MATLAB as AXI Master Simulation

Simulate MATLAB as AXI Master using the Vivado simulator.

Featured Examples

Access FPGA External Memory Using MATLAB as AXI Master

Use MATLAB as AXI Master to access the external DDR memories connected to the FPGA. In the FPGA, there is a Xilinx DDR memory controller instantiated for accessing the DDR memories. This memory controller provides an AXI4 slave interface for read and write operations by other components on the FPGA. The MATLAB as AXI Master feature provides an AXI master component that can be used to access any AXI slave IPs in the FPGA.

IP Core Generation Workflow without an Embedded ARM Processor: Xilinx Kintex-7 KC705

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example uses MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated DUT registers by enabling the reference design parameter option Insert JTAG MATAB as AXI Master. You can then access DUT registers from MATLAB directly. Alternatively, you can use Xilinx JTAG AXI Master to access the DUT registers using Vivado Tcl Console by writing Tcl commands. For Xilinx JTAG AXI Master, you need to create a custom reference design. The FPGA design is implemented on the Xilinx Kintex-7 KC705 board.

Performing Large Matrix Multiplication on FPGAs External DDR Memory Using Ethernet Based MATLAB as AXI Master

Use Ethernet-based MATLAB as AXI Master to access external memory connected to the FPGA. This example also shows how to:

Access FPGA External Memory Using Ethernet-Based MATLAB as AXI Master

Use Ethernet-based MATLAB as AXI Master to access the external memories connected to the FPGA. In the FPGA, there is a Xilinx DDR memory controller for accessing the DDR memories. This memory controller provides an AXI4 slave interface for read and write operations by other components in the FPGA. The Ethernet-based MATLAB as AXI Master feature provides an AXI master component that can be used to access any AXI slave IPs in the FPGA. In this example, we demonstrate how to integrate this Ethernet-based MATLAB as AXI Master into a Xilinx Vivado project, and read/write to the DDR memory using MATLAB.

Access FPGA External Memory Using MATLAB as AXI Master over PCI Express

Use MATLAB™ as AXI Master over PCI Express (PCIe) to access the external memory connected to an FPGA. The FPGA includes a Xilinx DDR memory controller for accessing the DDR memory. This memory controller provides an AXI4 slave interface for read and write operations by other components in the FPGA. The PCIe based MATLAB as AXI Master feature provides an AXI Master object that can be used to access any memory mapped location in the FPGA. This example shows how to integrate PCIe based MATLAB as AXI Master into a Xilinx Vivado project, and read or write to the DDR memory using MATLAB.

Leverage Built-In Ethernet on Zynq to Perform Memory Access Using AXI Master

Use an Ethernet-based MATLAB as AXI Master to access the external memory and FPGA IPs on the Xilinx Zynq®-7000 ZC706 board over Ethernet. In Xilinx Zynq-based designs, MATLAB® acts as an AXI Master and communicates with the external memory controller and FPGA IPs through an AXI Lite interface by using the user datagram protocol (UDP) server in the processing system (PS). The following block diagram shows the communication between a host and a Xilinx Zynq®-7000 board over Ethernet.

HDL Verifier Support Package for Xilinx FPGA Boards Documentation

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