ADAU1761 Codec

Connect hardware logic to ADAU1761 signals on hardware board

Since R2019a

• 

Libraries:
SoC Blockset Support Package for Xilinx Devices / Audio

Description

The ADAU1761 Codec block connects your hardware logic to the ADAU1781 codec on the hardware board. When you include this block in your design, the SoC Builder tool generates a constraint file to map the pins of the FPGA to the codec pins. Of the supported boards, only ZedBoard™ includes the ADAU1761 codec. This board uses the I2C interface to connect the FPGA and the audio codec, so your design must connect the ADAU1761 Codec block to an I2C Master block.

Ports

Input

SCL — I2C clock

Boolean scalar

I2C clock, specified as a Boolean scalar.

Data Types: Boolean

SDA — I2C data

Boolean scalar

I2C data, specified as a Boolean scalar.

Data Types: Boolean

ADDR0 — I2C address 0

Boolean scalar

I2C address 0, specified as a Boolean scalar. For HDL code generation, this port must be connected to a constant, true.

Data Types: Boolean

ADDR1 — I2C address 1

Boolean scalar

I2C address 1, specified as a Boolean scalar. For HDL code generation, this port must be connected to a constant, true.

Data Types: Boolean

SerialIn — DAC serial input data

Boolean scalar

Digital-to-analog converter (DAC) serial input data, specified as a Boolean scalar.

Data Types: Boolean

Output

SerialOut — ADC serial output data

Boolean scalar

Analog-to-digital converter serial output data, returned as a Boolean scalar.

Data Types: Boolean

BCLK — Serial port bit clock

Boolean scalar

Serial port bit clock, returned as a Boolean scalar.

Data Types: Boolean

LRCLK — Serial port frame clock

Boolean scalar

Serial port frame clock, returned as a Boolean scalar.

Data Types: Boolean

Extended Capabilities

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool.

Version History

Introduced in R2019a