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5G NR SIB1 Recovery for FR1 and FR2 Using Xilinx RFSoC Device

This example shows how to deploy a 5G NR SIB1 recovery algorithm for FR1 and FR2 in Simulink® using SoC Blockset® to target a Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board.

Supported Hardware Platforms

This example supports the Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit + XM500 Balun card

Introduction

This example implements a SIB1 recovery algorithm as a hardware-software (HW/SW) co-design implementation targeted to a Xilinx RFSoC device. This example is one of a related set. For more information see NR HDL Reference Applications Overview (Wireless HDL Toolbox).

This figure shows a conceptual overview of the SIB1 recovery algorithm.

The design is partitioned into sections for implementation on hardware and software.

  • SSB detection, SSB decoding, CORESET grid demodulation, PDCCH decoding, and LDPC decoding require high-speed signal processing. These parts of the design are well-suited for FPGA implementation and are targeted to the programmable logic (PL) on the RFSoC device. The model uses DSP HDL Toolbox™ and Wireless HDL Toolbox™ blocks to implement the FPGA signal processing algorithms.

  • The control and resource allocation calculations that the search controller, PDCCH software, and PDSCH software perform are low rate and well-suited for software implementation using the ARM® processing system (PS). Code generation from 5G Toolbox™ is used for functions calculating the PDCCH and PDSCH resource allocations, and the PDSCH channel estimation and equalization.

Setup

This example requires the SoC Blockset Support Package for Xilinx Devices. For more information on setup and configuration of the tools, see Setup and Configuration.

Top-Level Model

The top-level model, soc_nrhdlSIB1Recovery_top, shows the complete design. The model references the hardware and software models and shows the interfacing between the PL and PS. The model uses AXI-Stream and AXI-Lite interfaces to pass data between the PS and PL. The external DDR, which is used to store a waveform for testing the system, connects to the PL. The RF Data Converter block sets the parameters for the RF data converter on the hardware and connects to the PL.

When you run the model on the RFSoC hardware, the SIB1 receiver requires a 5G waveform from the ADCs in the RF data converter or a test waveform loaded to the external DDR memory. If you run the top-level model as a simulation, neither of these waveform sources is available, so the simulation uses data from the empty DDR memory and the SIB1 receiver does not find any 5G cells. To explore the behavior of the 5G SIB1 recovery algorithm, see the NR HDL SIB1 Recovery for FR2 (Wireless HDL Toolbox) example. For the design in this example to detect 5G SIB1, deploy it to a ZCU111 development board, and load a 5G test waveform into the DDR memory to provide a valid input to the receiver algorithm.

RF Data Converter Configuration

The RFSoC device has an RF data converter connected to the programmable logic. The RF Data Converter block configures the parameters of the RF data converter on the RFSoC hardware. The RF Data Converter configuration for the ZCU111 development board uses direct RF sampling to downconvert the RF signals. This configuration causes aliasing of any signals that are in lower Nyquist zones unless these signals are filtered out before the input to the ADCs. For this reason, external analogue filtering is required if you want to use the design with over-the-air 5G signals, or with loopback over the RF interface. Refer to the Xilinx product guide for the RFSoC Data Converter, Product Guide PG269, for more information.

The ADCs and DACs use a clock rate of 245.76MHz at the interface with the FPGA, with two samples per clock. This configuration results in a sample rate of 491.52 MHz. To achieve a sample rate of 3932.16 MHz at the ADC and the DAC, the RF Data Converter decimates and interpolates by a factor of 8. The RF Data Converter uses the DAC5 from Tile2 and ADC3 from Tile2, which correspond to connections J7 and J2 on the XM500 Balun card, respectively.

FPGA Logic Design

The soc_nrhdlSIB1Recovery_fpga Simulink model contains the FPGA part of the design. This model implements the SIB1 receiver hardware algorithm, AXI interfacing logic, and waveform playback from external memory as shown in the diagram. For more information about the SIB1 receiver hardware algorithm, see the NR HDL SIB1 Recovery (Wireless HDL Toolbox) and NR HDL SIB1 Recovery for FR2 (Wireless HDL Toolbox) examples. The AXI Stream interfacing subsystems format the data the FPGA sends to, and receives from, the embedded software part of the design.

The transmit-repeat subsystem soc_nrhdlSIB1Recovery_fpga/DUT/Transmit Repeat controls the input waveform to the NR receiver on the hardware.

The External Memory Access subsystem reads data from the external DDR memory using the input parameters specifying the memory base address, number of bursts, and last burst length to control the read process. Configure the input parameters for external memory access using the AXI-Lite input ports. When you enable the External Memory Access subsystem it loops through the data stored in the DDR, repeating the stored waveform. Use the DDR waveform used directly as an input to the SIB1 receiver or loop back through the DACs and ADCs in the RF data converter. You can use the loopback input to control waveform looping inside the Radio Interface subsystem. When you set loopback to 1 the waveform is loops back through the DACs and ADCs, provided you connect cables or antennas on the hardware to facilitate this.

You can also add noise and a frequency offset to the waveform by using the channelAWGNEn, channelNoisePow, and channelFrequencyOffset input ports. These impairments are added within the Channel subsystem. The Rate Convert subsystem passes the signals through without modification.

Processor Logic Design

The soc_nrhdlSIB1Recovery_proc Simulink model contains the software part of the design. This model implements the cell search control algorithm, PDCCH software processing, PDSCH software processing, and AXI interfacing logic to communicate with the FPGA.

This model has a mask to set parameters specific to the waveform and controlling waveform playback. Clicking on an instance of the model opens the Block Parameters dialog window. The parameters in this dialog window are set using variables in the base workspace. The model initializes the variables to zero. The variables are set to the appropriate values when you run socNRSIB1_externalModeSetup script with the design deployed on the target hardware.

The blocks in the Signals From FPGA section provide the AXI-Lite and AXI-Stream interfacing for the inputs to the software algorithm. The blocks in the Signals To FPGA section provide the AXI-Lite and AXI-Stream interfacing for the outputs from the software algorithm. The signals grouped in the axiLite to FPGA txRepeat subsystem are used to configure the waveform playback from DDR on the FPGA. The blocks in the UDP send to host section send selected data over UDP. Use the soc_nrhdlSIB1Recovery_hostUDPReceive model to receive this data.

The setupFreqDependantParams MATLAB function block initializes frequency-dependent parameters required for the software processing algorithm. The SSB subcarrier spacing, SSB block pattern, Lmax, and minimum channel bandwidth are dependent on the carrier frequency. Set useCentreFrequency input to TRUE to derive the parameters from the centreFrequency input port. Set useCentreFrequency to FALSE to use the parameters defined on the input ports. These parameters are available in the model mask. The model sets the initial parameter values to zero and updates them based on the test waveform generated using the socNRSIB1_externalModeSetup MATLAB script.

The axiStreamDemux subsystem demultiplexes the AXI-Stream data it receives from the FPGA. The data stream contains PSS reports, SSB grid data, SIB1 grid data, and SIB1 bits at different stages of the decoding process. The axiStreamDemux subsystem routes the data to the appropriate subsystems.

The Cell Search Controller subsystem controls the initial search for SSBs in the received waveform. This subsystem instructs the FPGA to search for SSBs at a given frequency offset and subcarrier spacing. When the FPGA completes the SSB search, it reports the results back to the software. The Cell Search Controller processes the results and selects an SSB for further decoding. For more information about the cell search process, see NR HDL Cell Search (Wireless HDL Toolbox).

The SIB1 SW Processing subsystem uses the SIB1 grid recovered by the FPGA and sent on the AXI-Stream interface. This subsystem locates the SIB1 resources within the SIB1 grid and, using hardware accelerators on the FPGA, decodes the DCI message from CORESET0 and decodes the SIB1 message. The subsystem formats the SIB1 grid to the required dimensions and locates the CORESET0 and PDCCH resources for SIB1 within the SIB1 grid. The subsystem sends CORESET0 resources to the FPGA over AXI-Stream. The hardware accelerator performs channel estimation and equalization, PDCCH, and polar decoding. The FPGA hardware accelerator returns the DCI data decoded form the CORESET0 to the software using AXI-Lite. The subsystem uses the DCI data to locate the PDSCH resources allocated to the SIB1 message. The subsystem performs channel estimation and equalization for the PDSCH data and passes the DLSCH codeword the FPGA hardware over AXI-Stream. The hardware accelerator performs rate recovery, LDPC, and CRC decoding.

When the FPGA successfully decodes the SIB1 message, it returns the SIB1 bits over the AXI-Stream interface. The sib1Error AXI-Lite input indicates whether the CRC detects any errors. The software returns the SIB1 bits to the host via the UDP interface.

Host Model

The run the soc_nrhdlSIB1Recovery_hostUDPReceive host model on the host computer to receive UDP messages from the deployed system when it is running on the RFSoC device.

Use the manual switch in the Stop Logic group of blocks to stop the model after receiving SIB1 bits, or to continue running until you stop the model manually. The model displays PSS SNR, SSS SNR, and decoded Cell ID. The MIB parameters and SIB1 bits are available as workspace variables.

Deploy Design

Open the soc_nrhdlSIB1Recovery_top model and set the Hardware Board option in the System on Chip tab of the Simulink toolstrip to Xilinx Zynq UltraScale+ RFSoC. Open SoC Builder by selecting Configure, Build, & Deploy from the System on Chip tab of the Simulink toolstrip.

  1. Select Build Model on the Setup screen. Click Next.

  2. Click View/Edit Memory Map to view the memory map on the Review Memory Map screen. Click Next.

  3. Specify the project folder on the Select Project Folder screen. Click Next.

  4. Select Build and load for external mode on the Select Build Action screen. Click Next.

  5. Click Validate on the Validate Model screen to check the compatibility of the model for implementation. Click Next.

  6. Click Build on the Build Model screen to begin building the model. An external shell opens when FPGA synthesis begins. This step can take a long time to complete. Click Next.

  7. Click Test Connection on the Connect Hardware screen to test the connectivity of the host computer with the SoC board. Click Next to go to the Run Application screen. Click Load to program the board with the bitstream.

After you load the bit file the board, you can run the generated software model in external mode to run the system on the board. If the generated software model is not already open, open soc_nrhdlSIB1Recovery_top_sw, which is in the project folder that you specify in the SoC Builder tool. Before you run the software on the board, you must load a waveform to the DDR memory. Run the socNRSIB1_externalModeSetup script to generate a waveform and write it to the DDR on the board using the JTAG interface. This script also initializes the variables in the software that specify parameters related to the waveform.

To perform loopback over the DAC and ADC interface on the hardware you must connect a cable between J7 and J2 on the XM500 balun card, with a 3000-4300 MHz bandpass filter in-line. You must also enable loopback in the mask of the software model reference in the soc_nrhdlSIB1Recovery_top_sw model by clicking on the sw_inst block and setting Enable loopback to 1. If you set Simulation mode in the dialog window to Accelerator then Enable loopback is run-time configurable. The other variables on this mask are set when you run socNRSIB1_externalModeSetup.

After you load a waveform to the DDR on the board, you can run the soc_nrhdlSIB1Recovery_top_sw model in external mode by selecting Monitor & Tune from the System on Chip tab of the Simulink toolstrip. By default, the model runs for 10 seconds. To modify the run time, set the Stop Time on the Simulink toolstrip. Use the Simulink Data Inspector to monitor logged signals in the software model while it is running and review the data once the model has stopped. This figure shows several logged signals from the software model when it successfully decodes SIB1. Hardware Start, SoftwareStart, and detectionStatus signals show the initial cell search process. The detectionStatus signal indicates the status of the cell search. A value of 8 indicates successful demodulation of MIB resource grid. The sib1Status signal shows the status of the SIB1 decoding process. A value of 5 indicates there were not errors detected in the CRC for SIB1. The value of sib1BitsValid indicates the SIB1 bits are sent from the FPGA to the software. The sib1Error signal indicates that no errors were found in the SIB1 CRC.

Run the soc_nrhdlSIB1Recovery_hostUDPReceive host model while the deployed software model is running to receive UDP messages containing the SIB1 bits, MIB parameters, and PSS and SSS reports.

Implementation Results

The table shows the post-implementation resource utilization results for the complete PL design, targeted to a ZCU111 evaluation board.

      Resource       Usage     Percentage
    _____________    ______    __________

    CLB Registers    182797       21%
    CLB LUTs         135024       32%
    RAMB18           431          20%
    RAMB36           74           7%
    DSP48            237          6%

See Also

Blocks