5G NR MIB Recovery Using Analog Devices AD9361/AD9364
This example shows how to deploy the MIB recovery algorithm from the NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox) example as a hardware-software (HW/SW) co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform. Using this implementation, you can perform MIB recovery from off-the-air 5G NR waveforms.
For a list of supported radio hardware platforms, see Hardware Support. Due to limited hardware resources, this example does not support Avnet ZedBoard and FMCOMMS2/3/4.
This example deploys a MIB recovery algorithm as a hardware-software (HW/SW) co-design implementation targeted on the Analog Devices AD9361/AD9364 radio platform. This example is one of a related set, for more information see NR HDL Reference Applications Overview (Wireless HDL Toolbox).
This figure shows a conceptual overview of the MIB recovery algorithm.
The SSB Detector and SSB Decoder perform the high-speed signal processing tasks required to detect, demodulate, and decode 5G NR synchronization signal blocks (SSB). This makes these parts well suited for FPGA implementation on the programmable logic (PL) of the radio platform. To implement the detector and decoder in the PL, the example uses model references of the Simulink hardware models from the NR HDL Cell Search (Wireless HDL Toolbox) and NR HDL MIB Recovery (Wireless HDL Toolbox) reference examples, respectively.
The Search Controller coordinates the operation of the detector and decoder hardware cores and operates at a low rate. This makes the search controller well suited for software implementation on the integrated ARM® processing system (PS) of the radio platform. The example uses the Search Controller algorithm described in the NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox) example.
To work with the HW/SW co-design workflow, you must install and configure additional support packages and third-party tools. For more information, see Installation for Hardware-Software Co-Design.
Hardware Generation Model
This Simulink model is a hardware generation model of the combined SSB Detector and SSB Decoder for targeting SDR platforms. From this model, you can generate HDL code for the PL and generate a template software interface model using HDL Workflow Advisor. Using the template software interface model, you can generate an application that runs on the PS. This diagram shows the hardware subsystem and a simple test harness.
The 5G MIB Recovery HDL subsystem adopts the MIB recovery model from the NR HDL MIB Recovery (Wireless HDL Toolbox) example and adds additional functionality to integrate the model with the Zynq® hardware architecture.
The Report Serializer subsystem generates primary synchronization signal (PSS) reports with the five numerical values of
The Custom Packetization MATLAB® function block formats the PSS reports into a custom packet format. This allows for sending over the receiver DMA to the search controller running on the ARM PS. Each standard-size packet consists of up to 48 PSS reports and an entry defining the number of valid reports in the packet.
Simulate Hardware Generation Model
To confirm basic operation, you can run the hardware generation model using a synthetic 5G NR waveform. You can generate a waveform using the
nrhdlexamples.generateFR1RxWaveform function. The model calls this function in the initialization callback and assigns the waveform to the workspace variable
burstWaveform. You can find the initialization callback in MODELING > Model Settings > Model Properties > Callbacks > InitFcn. As the model contains a large number of HDL-optimized blocks requiring simulation using sample-based signals, full simulation can take a while.
You can simulate the hardware generation model using the test harness. To model the RF front end, the test harness uses the generated 5G NR waveform as an input. You can switch between simulating the model in search or demodulation modes by double clicking on the manual switch block. In search mode, the model reaches
detectionStatus state 3, which means a PSS is found. The search produces a PSS report for each PSS found. These reports are zero-padded to 244 entries and logged to the MATLAB workspace. In demodulation mode, the model reaches
detectionStatus state 8 indicating that the SSB is demodulated and its secondary synchronisation signal (SSS) is found. Once the
detectionStatus reaches state 8, the model starts processing the MIB.
bchStatus state 4 indicates that the MIB is successfully recovered. The model also returns the demodulated OFDM grid in the MATLAB workspace as a variable of 960 entries (four symbols of 240 subcarriers). In addition, the model also returns the zero-padded 244-entry PSS report.
When the simulation behavior of the hardware subsystem is satisfactory, you can start the process of generating the HDL IP Core, integrating it with the SDR reference design, and generating software for the ARM processor.
Generate IP Core
Start the targeting workflow by right-clicking the 5G MIB Recovery HDL subsystem and selecting HDL Code > HDL Workflow Advisor.
In Step 1.1, select the
IP Core Generationworkflow and the appropriate Zynq radio platform:
ADI RF SOM,
ZC706 and FMCOMMS2/3/4,
ZCU102 and FMCOMMS2/3/4, or
ZC706 and FMCOMMS5. Due to limited hardware resources, this example does not support ZedBoard and FMCOMMS2/3/4.
In Step 1.2, select the
Receive pathreference design. For this example, you can use default reference design parameters.
In Step 1.3, the interface table maps the DUT signals to the interface signals available in the reference design. Because this example uses a single channel, configure the channel 1 connections and AXI register interfaces as shown in these images.
In Step 1.4, set the DUT synthesis frequency. The DUT synthesis frequency depends on the baseband sampling rate of the system. The MIB Recovery algorithm implementation in this example is built for a sampling rate value of 61.44 MHz.
Step 2 prepares the model for HDL code generation by performing design checks.
Step 3 generates HDL code for the IP core.
Generate Software Interface Model and Block Library
Step 4 of the HDL Workflow Advisor integrates the newly generated IP core into the Zynq SDR reference design, generates the corresponding bitstream, and loads the bitstream onto the board.
Step 4.2 generates a software interface library and a template software interface model.
Software Interface Library
The library contains the AXI Interface block generated from the
5G MIB Recovery HDL subsystem and a receiver block corresponding to your hardware you selected in Step 1.1. The data ports of the receiver block represent the DMA interface between the FPGA user logic and the ARM processor. The DMA interface is used to stream the four demodulated OFDM symbols to the ARM processor after a demodulation attempt. Each symbol consists of 240 subcarriers and therefore the frame size is set to 960.
To stream the SSB grid from the MIB Recovery algorithm (running on hardware) to the search controller algorithm (running on software), the model utilizes an AXI4-Stream interface. The AXI4-Stream IIO Read (Embedded Coder) block which implements the AXI4-Stream interface in the software interface model is not generated in the template or library. You must add the block from the Simulink Library Browser > Embedded Coder Support Package for Xilinx Zynq Platform library.
When using the library blocks in a downstream model, you must configure the parameters correctly for your application. Take into account that any updates to the
5G MIB Recovery HDL subsystem are automatically propagated to the library blocks in the downstream model when you run Step 4.2 again.
Template Software Interface Model
You can use the generated template software interface model as a starting point for full SW targeting in, for example, external mode simulation, or full deployment. Because HDL Workflow Advisor overwrites the generated model each time you run Step 4.2, consider saving the generated model under a unique name and develop your software algorithm there.
Generate and Load Bitstream
The last steps of the HDL Workflow Advisor generate a bitstream for the PL and download the bitstream onto the board.
Step 4.3 generates a bitstream for the PL. You can execute this step in an external shell by selecting Run build process externally. This selection allows you to continue using MATLAB while building the FPGA image. Once some basic project checks are complete, Step 4.3 is marked with a green checkmark. However, you must wait until the external shell displays a successful bitstream build before moving on to the next step.
Step 4.4 downloads the bitstream onto the device. Before continuing with this step, make sure that MATLAB is set up with the correct physical IP address of the radio hardware by calling the
>> devzynq = zynq('linux','192.168.3.2','root','root','/tmp');
By default, the physical IP address of the radio hardware is 192.168.3.2. If you alter the radio hardware IP address during the hardware setup process, you must supply that address instead.
Alternatively, if you want to load the bitstream outside HDL Workflow Advisor, create an SDR radio object and use the
downloadImage function. The radio object to create depends on the radio platform selected in Step 1.1.
If the selected radio platform is either
ADI RF SOM,
ZC706 and FMCOMMS2/3/4, or
ZCU102 and FMCOMMS2/3/4, create an AD936x radio object.
>> radio = sdrdev('AD936x');
If the selected radio platform is
ZC706 and FMCOMMS5, create an FMCOMMS5 radio object.
>> radio = sdrdev('FMCOMMS5');
Download the bitstream using the radio object interfacing the selected radio device.
>> downloadImage(radio,'FPGAImage', ... 'hdl_prj\vivado_ip_prj\vivado_prj.runs\impl_1\system_top.bit') % Path to the generated bitstream
5G NR MIB Recovery Software Interface Model
The 5G NR MIB Recovery interface model is based on the generated template software interface model. The model coordinates the MIB recovery, as described in the NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox) example. The Cell Search Controller block in the searchControl subsystem controls the deployed hardware model by using the AXI4-Lite and AXI4-Stream interfaces inside the MIB Recovery subsystem. The setupFreqDependantParams block in the searchControl subsystem configures the set of permitted subcarrier spacings, SSB patterns, and
Lmax based on the carrier frequency, as defined in the 5G standard.
The Signal Quality Measurements subsystem measures the received signal strength indicator (RSSI), reference signal received power (RSRP), reference signal received quality (RSRQ), and signal to interference & noise ratio (SINR) of the SSS for each valid SSB grid.
The UDP send grid, UDP send PSS report, UDP send SSS report, UDP send MIB report, and UDP send Signal Quality Measurements subsystems relay the demodulated OFDM grid data, PSS report, SSS report, MIB report, and SSB signal quality measurements, respectively, to the host by using the UDP protocol.
The model is configured for the
Xilinx Zynq-7000 Based Board target. You can use this target for the
ADI RF SOM or
ZC706 and FMCOMMS2/3/4/5 radio platforms. For the
ZCU102 and FMCOMMS2/3/4 radio platform, you must reconfigure the model by selecting
Zynq UltraScale+ MPSoC ZCU102 IIO Radio in Model Settings (Ctrl+E) > Hardware Implementation > Hardware board or by double clicking the provided
Select Hardware Board Target block.
You can use the scopes from the software interface model to monitor the hardware and software. The
Algorithm Scope plots the progress of the cell search algorithm. The periodic software start signal begins each operation. The controller then instructs the PL to perform SSB detection in search mode (Hardware Mode 0) for each coarse frequency step and subcarrier spacing. The scope shows how the Frequency Offset and Subcarrier Spacing signals are set for each search attempt and how the Hardware Start signal is pulsed to begin. The software selects a coarse frequency offset and subcarrier spacing based on the PSS correlation strength and residual fine frequency offset of detected SSBs. Then a final search runs with the combined coarse and fine frequency corrections. Next, a demod mode (Hardware Mode 1) operation starts. This attempts to reacquire the best SSB from the previous search, demodulate the resource grid, and compute the cell ID from the SSS sequence. Once the
detectionState reaches 8, the hardware decodes the SSB. The
decodingState then reaches state 4, indicating successful decoding. For more information about the algorithm, see NR HDL Downlink Receiver MATLAB Reference (Wireless HDL Toolbox). In some instances, the hardware state can change faster than the polling of the AXI-Lite registers.
A large amount of data is available for analysis on the PS. In this example, the
MIB scopes display a selection of additional information. To view signals of interest, you can customize the
Data Logging area. For further exploration, you can add postprocessing subsystems to perform live analysis of the returned signals.
Run Design on Zynq Board
You can run the 5G NR MIB Recovery software interface model in
Monitor & Tune mode. In this mode, you can control the configuration from the Simulink model. Alternatively, to deploy the design on the board disconnected from Simulink, click
Build Deploy & Start.
The default center frequency for this example is 3560 MHz. You can adjust the center frequency by using the
Center Frequency constant block.
Start/Restart Pulse Generator block resets the cell search controller algorithm with a period of 0.6 seconds.
Host Interface Model
The ARM sends the demodulated OFDM grid data, PSS reports, SSS reports, MIB reports, and signal quality measurements back to the host over the Ethernet link by using UDP send blocks. The IP address of the UDP send block must be the IP address of the host, by default, '192.168.3.1'. If you alter the IP address during the hardware setup process, you should supply that address instead.
This interface model, which runs on the host, illustrates how to receive data from the hardware platform and how to postprocess it. You can use the rocker switch to select between automatically stopping the model after MIB is recovered or to receive indefinitely.
When the host interface model successfully runs, the model displays the received signal-to-noise ratio (SNR) of the PSS and SSS in dB, the cell ID, the signal quality measurements of the SSB, and the contents of the recovered MIB. While the model continuously runs, the MIB count increments for each successful recovery.
For further processing, the model also exports four timeseries variables to the MATLAB workspace:
If you are unable to receive a strong 5G signal in your location, consider performing a loopback of the generated waveform by using the
transmitRepeat function. To detect SSBs and to recover MIB using synthesized waveforms, ensure that carrier frequency dependent parameters, such as the SSB subcarrier spacing, SSB block pattern, Lmax, and minimum channel bandwidth, match the carrier frequency set in the software interface model.
% Generate 5G waveform [txWaveform,~,~] = nrhdlexamples.generateFR1RxWaveform('SimCase 1'); % Create a transmitter System object for the AD936x-based radio hardware and set desired radio settings. tx = sdrtx('AD936x', 'CenterFrequency', 3560e6, 'BasebandSampleRate', 61.44e6, 'IPAddress', '192.168.3.2'); % Send waveform to the radio and repeatedly transmit it. transmitRepeat(tx,txWaveform);
The host interface model returns the demodulated OFDM grid data to the MATLAB workspace. If you have a strong signal, consider plotting this grid. For example:
gridFormatData = squeeze(sl_grid.Data); y = reshape(gridFormatData(:,1),[240,4]); gridData = double(abs(y)); OFDMGridFigure = figure('Name','OFDM Grid'); axes1 = axes('Parent',OFDMGridFigure); hold(axes1,'on'); imagesc(gridData,'Parent',axes1,'CDataMapping','scaled'); ylabel('Subcarrier'); xlabel('OFDM Symbol'); title('5G NR OFDM Demodulated Grid'); box(axes1,'on'); axis(axes1,'ij'); hold(axes1,'off'); set(axes1,'Layer','top',... 'XTick',[1 2 3 4],'YTick',[1 40 80 120 160 200 240], ... 'Xlim',[0.5,4.5],'YLim', [1, 240]); colorbar(axes1,'Position',... [0.92 0.11 0.01 0.82]);