CLB X-BAR
The CLB X-BAR brings signals to the CLB modules. The CLB X-BAR has eight outputs which are routed to each CLB module.
Note
The F2807x, F2837x, F28002x, F28004x, F28003x, F2838x and F28P65x processors support CLB X-BAR. For more information, refer to TI Technical Reference Manual of there respective processors.
- AUXSIG# MUX select
Select the MUX to map the signal to the MUX AUXSIG#. AUXSIG# (# can take values 0 to 7)
You can select up to one signal per mux (maximum available up to of 31 muxes) for each AUXSIG# output. AUXSIG# MUX select values are based on the processor selected.
Selecting
Disable allwill indicate that all MUXes are disabled and the CLB X-BAR# is not configured.Note
AUXSIG# MUX select will not have MUX entries whose inputs are all reserved.
- Select MUX input
Select the signal to the MUX selected in
AUXSIG# MUX select. Ensure the selected MUX input peripheral is enabled and utilized.Select the input signals for the MUX which is sent to the CLB. You can select one signal per MUX. The input signal to the MUX varies based on the MUX selected and processor.
The following table lists the AUXSIG# MUX select and Select MUX input for C28x processor F2838x. The row headers 0-3 represent the Select MUX input and column headers 0-31 represent the AUXSIG# MUX select.
CLB X-BAR Mux Configuration Table - F2838x
Select MUX INPUT 
0 1 2 3 AUXSIG# MUX select 
0 CMPSS1.CTRIPH CMPSS1.CTRIPH_OR_CTRIP ADCAEVT1 ECAP1.OUT 1 CMPSS1.CTRIPL INPUTXBAR1 CLB1_OUT4 ADCCEVT1 2 CMPSS2.CTRIPH CMPSS2.CTRIPH_OR_CTRIP ADCAEVT2 ECAP2.OUT 3 CMPSS2.CTRIPL INPUTXBAR2 CLB1_OUT5 ADCCEVT2 4 CMPSS3.CTRIPH CMPSS3.CTRIPH_OR_CTRIP ADCAEVT3 ECAP3.OUT 5 CMPSS3.CTRIPL INPUTXBAR3 CLB2_OUT4 ADCCEVT3 6 CMPSS4.CTRIPH CMPSS4.CTRIPH_OR_CTRIP ADCAEVT4 ECAP4.OUT 7 CMPSS4.CTRIPL INPUTXBAR4 CLB2_OUT5 ADCCEVT4 8 CMPSS5.CTRIPH CMPSS5.CTRIPH_OR_CTRIP ADCBEVT1 ECAP5.OUT 9 CMPSS5.CTRIPL INPUTXBAR5 CLB3_OUT4 ADCDEVT1 10 CMPSS6.CTRIPH CMPSS6.CTRIPH_OR_CTRIP ADCBEVT2 ECAP6.OUT 11 CMPSS6.CTRIPL INPUTXBAR6 CLB3_OUT5 ADCDEVT2 12 CMPSS7.CTRIPH CMPSS7.CTRIPH_OR_CTRIP ADCBEVT3 ECAP7.OUT 13 CMPSS7.CTRIPL ADCSOCA CLB4_OUT4 ADCDEVT3 14 CMPSS8.CTRIPH CMPSS7.CTRIPH_OR_CTRIP ADCBEVT4 EXTSYNCOUT 15 CMPSS8.CTRIPL ADCSOCB CLB4_OUT5 ADCDEVT4 16 SD1FLT1.COMPH SD1FLT1.COMPH_OR_ COMPL SD1FLT1.COMPZ SD1FLT1.DRINT 17 SD1FLT1.COMPL INPUTXBAR7 CLB5_OUT4 CPU1.CLA1HALT 18 SD1FLT2.COMPH SD1FLT2.COMPH_OR_ COMPL SD1FLT2.COMPZ SD1FLT2.DRINT 19 SD1FLT2.COMPL INPUTXBAR8 CLB5_OUT5 Reserved 20 SD1FLT3.COMPH SD1FLT3.COMPH_OR_ COMPL SD1FLT3.COMPZ SD1FLT3.DRINT 21 SD1FLT3.COMPL INPUTXBAR9 CLB6_OUT4 Reserved 22 SD1FLT4.COMPH SD1FLT4.COMPH_OR_ COMPL SD1FLT4.COMPZ SD1FLT4.DRINT 23 SD1FLT4.COMPL INPUTXBAR10 CLB6_OUT5 EMAC.PPS1 24 SD2FLT1.COMPH SD2FLT1.COMPH_OR_ COMPL SD2FLT1.COMPZ SD2FLT1.DRINT 25 SD2FLT1.COMPL INPUTXBAR11 MCANA.FEVT0 CLB7_OUT4 26 SD2FLT2.COMPH SD2FLT2.COMPH_OR_ COMPL SD2FLT2.COMPZ SD2FLT2.DRINT 27 SD2FLT2.COMPL INPUTXBAR12 MCANA.FEVT1 CLB7_OUT5 28 SD2FLT3.COMPH SD2FLT3.COMPH_OR_ COMPL SD2FLT3.COMPZ SD2FLT3.DRINT 29 SD2FLT3.COMPL INPUTXBAR13 MCANA.FEVT2 CLB8_OUT4 30 SD2FLT4.COMPH SD2FLT4.COMPH_OR_ COMPL SD2FLT4.COMPZ SD2FLT4.DRINT 31 SD2FLT4.COMPL INPUTXBAR14 EMAC.PPS0 CLB8_OUT5 CLB X-BAR Mux Configuration Table - F28003x
Select MUX INPUT 0 1 2 3 AUXSIG# MUX select 0 CMPSS1.CTRIPH CMPSS1.CTRIPH_OR_CTRIP ADCAEVT1 ECAP1.OUT 1 CMPSS1.CTRIPL INPUTXBAR1 CLB1_OUT4 ADCCEVT1 2 CMPSS2.CTRIPH CMPSS2.CTRIPH_OR_CTRIP ADCAEVT2 ECAP2.OUT 3 CMPSS2.CTRIPL INPUTXBAR2 CLB1_OUT5 ADCCEVT2 4 CMPSS3.CTRIPH CMPSS3.CTRIPH_OR_CTRIP ADCAEVT3 ECAP3.OUT 5 CMPSS3.CTRIPL INPUTXBAR3 CLB2_OUT4 ADCCEVT3 6 CMPSS4.CTRIPH CMPSS4.CTRIPH_OR_CTRIP ADCAEVT4 ECAP4.OUT 7 CMPSS4.CTRIPL INPUTXBAR4 CLB2_OUT5 ADCCEVT4 8 Reserved Reserved ADCBEVT1 Reserved 9 Reserved INPUTXBAR5 CLB3_OUT4 Reserved 10 Reserved Reserved ADCBEVT2 Reserved 11 Reserved INPUTXBAR6 CLB3_OUT5 Reserved 12 Reserved Reserved ADCBEVT3 Reserved 13 Reserved ADCSOCAO CLB4_4 Reserved 14 Reserved Reserved ADCBEVT4 EXTSYNCOUT 15 Reserved ADCSOCBO CLB4_5 Reserved 16 SD1FLT1.COMPH SD1FLT1.COMPH_OR_ COMPL SD1FLT1.COMPZ SD1FLT1.DRINT 17 SD1FLT1.COMPL INPUTXBAR7 Reserved CPU1.CLA1HALT 18 SD1FLT2.COMPH SD1FLT2.COMPH_OR_ COMPL SD1FLT2.COMPZ SD1FLT2.DRINT 19 SD1FLT2.COMPL INPUTXBAR8 Reserved ERRORSTS ERROR 20 SD1FLT3.COMPH SD1FLT3.COMPH_OR_ COMPL SD1FLT3.COMPZ SD1FLT3.DRINT 21 SD1FLT3.COMPL INPUTXBAR9 Reserved Reserved 22 SD1FLT4.COMPH SD1FLT4.COMPH_OR_ COMPL SD1FLT4.COMPZ SD1FLT4.DRINT 23 SD1FLT4.COMPL INPUTXBAR10 Reserved Reserved 24 SD2FLT1.COMPH SD2FLT1.COMPH_OR_ COMPL SD2FLT1.COMPZ SD2FLT1.DRINT 25 SD2FLT1.COMPL INPUTXBAR11 MCANA.FEVT0 Reserved 26 SD2FLT2.COMPH SD2FLT2.COMPH_OR_ COMPL SD2FLT2.COMPZ SD2FLT2.DRINT 27 SD2FLT2.COMPL INPUTXBAR12 MCANA.FEVT1 Reserved 28 SD2FLT3.COMPH SD2FLT3.COMPH_OR_ COMPL SD2FLT3.COMPZ SD2FLT3.DRINT 29 SD2FLT3.COMPL INPUTXBAR13 MCANA.FEVT2 Reserved 30 SD2FLT4.COMPH SD2FLT4.COMPH_OR_ COMPL SD2FLT4.COMPZ SD2FLT4.DRINT 31 SD2FLT4.COMPL INPUTXBAR14 ERRORSTS ERROR Reserved CLB X-BAR Mux Configuration Table - F28004x
Select MUX INPUT 0 1 2 3 AUXSIG# MUX select 0 CMPSS1.CTRIPOUTH CMPSS1.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT1 ECAP1OUT 1 CMPSS1.CTRIPOUTL INPUTXBAR1 CLB1_OUT4 ADCCEVT1 2 CMPSS2.CTRIPOUTH CMPSS2.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT2 ECAP2OUT 3 CMPSS2.CTRIPOUTL INPUTXBAR2 CLB1_OUT5 ADCCEVT2 4 CMPSS3.CTRIPOUTH CMPSS3.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT3 ECAP3OUT 5 CMPSS3.CTRIPOUTL INPUTXBAR3 CLB2_OUT4 ADCCEVT3 6 CMPSS4.CTRIPOUTH CMPSS4.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT4 ECAP4OUT 7 CMPSS4.CTRIPOUTL INPUTXBAR4 CLB2_OUT5 ADCCEVT4 8 CMPSS5.CTRIPOUTH CMPSS5.CTRIPOUTH_OR_CTRIPOUTL ADCBEVT1 ECAP5OUT 9 CMPSS5.CTRIPOUTL INPUTXBAR5 CLB3_OUT4 Reserved 10 CMPSS6.CTRIPOUTH CMPSS6.CTRIPOUTH_OR_CTRIPOUTL ADCBEVT2 ECAP6OUT 11 CMPSS6.CTRIPOUTL INPUTXBAR6 CLB3_OUT5 Reserved 12 CMPSS7.CTRIPOUTH CMPSS7.CTRIPOUTH_OR_CTRIPOUTL ADCBEVT3 ECAP7OUT 13 CMPSS7.CTRIPOUTL ADCSOCAO CLB4_OUT4 Reserved 14 Reserved Reserved ADCBEVT4 EXTSYNCOUT 15 Reserved ADCSOCBO CLB4_OUT5 Reserved 16 SD1FLT1.COMPH SD1FLT1.COMPH_OR_COMPL Reserved Reserved 17 SD1FLT1.COMPL Reserved Reserved CLAHALT 18 SD1FLT2.COMPH SD1FLT2.COMPH_OR_COMPL Reserved Reserved 19 SD1FLT2.COMPL Reserved Reserved Reserved 20 SD1FLT3.COMPH SD1FLT3.COMPH_OR_COMPL Reserved Reserved 21 SD1FLT3.COMPL Reserved Reserved Reserved 22 SD1FLT4.COMPH SD1FLT4.COMPH_OR_COMPL Reserved Reserved 23 SD1FLT4.COMPL Reserved Reserved Reserved CLB X-BAR Mux Configuration Table - F28002x
Select MUX INPUT 0 1 2 3 AUXSIG# MUX select 0 CMPSS1.CTRIPOUTH CMPSS1.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT1 ECAP1OUT 1 CMPSS1.CTRIPOUTL INPUTXBAR1 CLB1_OUT4 ADCCEVT1 2 CMPSS2.CTRIPOUTH CMPSS2.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT2 ECAP2OUT 3 CMPSS2.CTRIPOUTL INPUTXBAR2 CLB1_OUT5 ADCCEVT2 4 CMPSS3.CTRIPOUTH CMPSS3.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT3 ECAP3OUT 5 CMPSS3.CTRIPOUTL INPUTXBAR3 CLB2_OUT4 ADCCEVT3 6 CMPSS4.CTRIPOUTH CMPSS4.CTRIPOUTH_OR_CTRIPOUTL ADCAEVT4 Reserved 7 CMPSS4.CTRIPOUTL INPUTXBAR4 CLB2_OUT5 ADCCEVT4 9 Reserved INPUTXBAR5 Reserved Reserved 11 Reserved INPUTXBAR6 Reserved Reserved 13 Reserved ADCSOCAO Reserved Reserved 14 Reserved Reserved Reserved EXTSYNCOUT CLB X-BAR Mux Configuration Table - F2807x/F2837xS/F2837xD
Select MUX INPUT 0 1 2 3 AUXSIG# MUX select 0 CMPSS1.CTRIPH CMPSS1.CTRIPH_OR_CTRIPL
ADCAEVT1 ECAP1.OUT 1 CMPSS1.CTRIPL INPUTXBAR1 CLB1_OUT4 ADCCEVT1 2 CMPSS2.CTRIPH CMPSS2.CTRIPH_OR_CTRIPL
ADCAEVT2 ECAP2.OUT 3 CMPSS2.CTRIPL INPUTXBAR2 CLB1_OUT5 ADCCEVT2 4 CMPSS3.CTRIPH CMPSS3.CTRIPH_OR_CTRIPL
ADCAEVT3 ECAP3OUT 5 CMPSS3.CTRIPL INPUTXBAR3 CLB2_OUT4 ADCCEVT3 6 CMPSS4.CTRIPH CMPSS4.CTRIPH_OR_CTRIPL
ADCAEVT4 ECAP4.OUT 7 CMPSS4.CTRIPL INPUTXBAR4 CLB2_OUT5 ADCCEVT4 8 CMPSS5.CTRIPH CMPSS4.CTRIPH_OR_CTRIPL
ADCBEVT1 ECAP5.OUT 9 CMPSS5.CTRIPL INPUTXBAR5 CLB3_OUT4 ADCCEVT1 10 CMPSS6.CTRIPH CMPSS4.CTRIPH_OR_CTRIPL
ADCBEVT1 ECAP6.OUT 11 CMPSS6.CTRIPL INPUTXBAR6 CLB3_OUT5 ADCCEVT2 12 CMPSS7.CTRIPH CMPSS7.CTRIPH_OR_CTRIPL
ADCBEVT3 Reserved 13 CMPSS7.CTRIPL ADCSOCAO CLB4_OUT4 ADCDEVT3 14 CMPSS8.CTRIPH CMPSS8.CTRIPH_OR_CTRIPL
ADCBEVT4 EXTSYNCOUT 15 CMPSS8.CTRIPL ADCSOCB CLB4_OUT5 ADCDEVT4 16 SD1FLT1.COMPH SD1FLT1.COMPH_OR_COMPL
Reserved Reserved 17 SD1FLT1.COMPL Reserved Reserved Reserved 18 SD1FLT2.COMPH SD1FLT2.COMPH_OR_COMPL
Reserved Reserved 19 SD1FLT2.COMPL Reserved Reserved Reserved 20 SD1FLT3.COMPH SD1FLT3.COMPH_OR_COMPL
Reserved Reserved 21 SD1FLT3.COMPL Reserved Reserved Reserved 22 SD1FLT4.COMPH SD1FLT4.COMPH_OR_COMPL
Reserved Reserved 23 SD1FLT4.COMPL Reserved Reserved Reserved 24 SD2FLT1.COMPH SD2FLT1.COMPH_OR_COMPL
Reserved Reserved 25 SD2FLT1.COMPL Reserved Reserved Reserved 26 SD2FLT2.COMPH SD2FLT2.COMPH_OR_COMPL
Reserved Reserved 27 SD2FLT2.COMPL Reserved Reserved Reserved 28 SD2FLT3.COMPH SD2FLT3.COMPH_OR_COMPL
Reserved Reserved 29 SD2FLT3.COMPL Reserved Reserved Reserved 30 SD2FLT4.COMPH SD2FLT4.COMPH_OR_COMPL
Reserved Reserved 31 SD2FLT4.COMPL Reserved Reserved Reserved For F2837x and F2807x processors CLB clock comes from ePWM clock. And for F2837xD, if both CLB and ePWM are used then they should be in same CPU.
- AUXSIG# MUX (MUX 0 -> 31)
Indicates the input signal selected for each output# MUX. For example,
XXXX1XXXXXXXXXXXXXXXXXXXXXXXXXXindicates that input signal 1 was selected for MUX 4.Xindicates that the MUX is disabled and no signal from the MUX will be sent to the CLB X-BAR.All the signals which are selected will be logically OR'd before being passed on to the respective AUXSIG#x signal on the CLB.
- RESET AUXSIG# MUX
Resets the signal selection for the MUX done so far.
Resets the AUXSIG# MUX (MUX 0->31) and Select MUX input inputs.
- Invert AUXSIG#
Select to invert the auxiliary signal on the CLB.
