This example shows how to interface with bursty pixel streams, such as those from DMA and Camera Link® sources, using the Pixel Stream FIFO block.
The DMACameraSourceHDL.slx system is shown below.
There are two pixel input streams - DMA source and Camera Link source. Input data for both sources is loaded from a
.mat file, in the
InitFcn callback. The DMA source models a non-contiguous stream of data arriving from off-chip memory. The pixels arrive in short bursts of random length, with random gaps between bursts. This can occur when there is contention on the DMA source and so it is not possible to stream pixels continuously from off-chip memory. The Camera Link source models the case when the camera is streaming an image of a lower resolution than the maximum permitted by the pixel clock and therefore will leave regular gaps between valid pixels. This spacing allows for streaming of multiple resolution images using a common clock, via strobing of validIn.
The Camera Link source models the incoming video stream from the sensor. The DMA source models a video stream from a frame buffer in which previous frame data has been processed in order to produce an alpha channel, allowing for blending of previous frame data with the current stream.
The Pixel Stream Overlay subsystem is shown in the diagram below. You can generate HDL code from this subsystem.
There are four main processing stages in the model - buffering of input data to remove burstiness, edge detection and overlay on Camera Link stream, alignment of pixel streams, and alpha blending of DMA stream onto Camera Link stream.
The Pixel Stream FIFO blocks buffer the input data as it is streamed into the model. The Pixel Stream FIFO is a masked subsystem. Looking into the Pixel Stream FIFO, we can see that it consists of a Memory Controller, Read and Write counters and two RAMs. One RAM stores the incoming pixel stream, and the other stores the incoming control signal stream. Once a full line has been buffered in RAM, the line is output continuously, removing any bursty behavior seen at input.
This waveform illustrates the difference in the pixel control signals after the Pixel Stream FIFO. The input
DMA_ControlIn(5), shows short bursts of valid pixels, while the output
DMA_ctrlClean(5), shows a continuous line of valid pixels. The total cycles in each line, shown by the time between
hStart assertions, remains the same.
To further differentiate the pixel streams, the Camera Link stream has an edge detection and overlay section. The pixel stream is first pre-processed by the Bilateral Filter block. This block smooths the image while preserving edges, and so it is a good choice for noise suppression prior to edge detection. The Edge Detector block detects edges using the Sobel method. The edges are then thinned using a [2x2] erosion operation. The thinned edge image is overlaid onto the original Camera Link image.
The Camera Link and DMA pixel streams must now be aligned to account for algorithmic delay in the data path. Aligning the pixel streams is straightforward using the Pixel Stream Aligner block.
The DMA input stream is a [1x4] vector whereas the Camera Link input is a [1x3] vector. The extra column in the DMA input is used to store the alpha channel information. The alpha channel represents the amount by which each of the pixels from the DMA source should be blended with the incoming Camera Link stream.
The output video stream shows the DMA stream alpha blended onto the Camera Link input. The magenta colored overlay indicates the edges detected in the incoming Camera Link stream.
To check and generate the HDL code referenced in this example, you must have an HDL Coder™ license.
To generate the HDL code, use the following command:
makehdl('DMACameraSourceHDL/Pixel Stream Overlay');
To generate an HDL test bench, use the following command:
makehdltb('DMACameraSourceHDL/Pixel Stream Overlay');