Modeling External Memory

You can model external memory using features from SoC Blockset™. These features provide models for a frame buffer or a random access interface and map your subsystem ports to physical AXI memory interfaces when you generate HDL code and target a prototype board.

You can use SoC Blockset library blocks to model a memory controller and multiple memory channels. This model calculates and visualizes memory bandwidth, burst counts, and transaction latencies in simulation. You can also model memory accesses from a processor as part of hardware-software co-design. Use the SoC Builder app to generate code for FPGA and processor designs and load and run the design on a board. You can also deploy an AXI memory interconnect monitor on your FPGA, which can return memory transaction information for debugging and visualization in Simulink^®. This level of modeling helps you verify throughput and latency requirements and enables modeling of multiple memory consumers, including processor memory access. For more information, see Memory (SoC Blockset).

Frame Buffer

This figure shows part of the Histogram Equalization Using Video Frame Buffer (SoC Blockset) example. The example shows how to use the AXI4 Video Frame Buffer library block to model a frame buffer and an optional Memory Traffic Generator block to model memory contention from another consumer. You can use this model to confirm that the memory interface meets the throughput and latency requirements of your design. You can measure the bandwidth and transaction latency for each memory consumer and check the measurements against the total bandwidth available from the memory.

Random Access

This figure shows part of the Random Access of External Memory (SoC Blockset) example. This design uses a AXI4 Random Access Memory block to implement a random-access interface. In this case, rather than connecting the pixel stream to the memory interface, your custom FPGA logic must generate read and write transactions with specific addresses.