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Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

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I recently connected the FFT Block in Simulink to in and out ports so i can generate its HDL Code and implement it in Vivado.
After i generated it, i compiled the files in Vivado and created a block design to connect its inputs and outputs to other components of my design, but first i wanted to test if it's even working so i connected the data_in port to a simple counter and ran the simulation.
The output was unfortunately just a bunch of zeros (bit vector of 19 zeros).
Any idea why it behaves like this ?
(clk connected to clocking wizard, reset connected to "1" as a constant and so are valid_in and clk_enable also).
This screenshot is from Vivado's Block Design but this FFT IP's source is Simulinks/Matlab's generated HDL code of the FFT HDL Optimized Block.

Accepted Answer

Bharath Venkataraman
Bharath Venkataraman on 23 Aug 2021
I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly.
The next thing is to check and make sure that you are feeding in the correct data via data_in and that valid_in is staying high for the FFT length. Also, note that FFT has a latency, so the output will stay at 0s for a certain number of clock cycles after the last input of the frame is passed in.
Hope this helps.
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