I recently connected the FFT Block in Simulink to in and out ports so i can generate its HDL Code and implement it in Vivado.
After i generated it, i compiled the files in Vivado and created a block design to connect its inputs and outputs to other components of my design, but first i wanted to test if it's even working so i connected the data_in port to a simple counter and ran the simulation.
The output was unfortunately just a bunch of zeros (bit vector of 19 zeros).
Any idea why it behaves like this ?
(clk connected to clocking wizard, reset connected to "1" as a constant and so are valid_in and clk_enable also).
This screenshot is from Vivado's Block Design but this FFT IP's source is Simulinks/Matlab's generated HDL code of the FFT HDL Optimized Block.