Do we have a standard procedure to convert SIMULINK model to HDL code?

I have developed a SIMULINK model of IPMSM based drive that uses FOC logic for torque control.

I want to convert the model to HDL code.

Answer 1

[Steven Lord]

Do you have HDL Coder licensed and installed? If so see the documentation and the examples link on that documentation page.

Answer 2

[Kiran Kintali]

HDL Coder Evaluation Reference Guide

https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide

Field-Oriented Control of a Permanent Magnet Synchronous Machine

https://www.mathworks.com/help/hdlcoder/ug/field-oriented-control-of-a-permanent-magnet-synchronous-machine.html

Floating Point Support: Field-Oriented Control Algorithm

https://www.mathworks.com/help//hdlcoder/ug/single-precision-field-oriented-control-pmsm-model.html

Simscape FPGA based Hardware-in-the-Loop Workflow

https://www.mathworks.com/help/hdlcoder/simscape-to-hdl.html

[Steven Zeng]

Hi Kiran, I have tried the Field-Oriented Control of a Permanent Magnet Synchronous Machine and change around the Code generation setting for testing. If I specify the [Target and Optimizations]>[Objectives Settings]>[Target Frequency] as well as the Synthesisi Tool, it will generate adaptive piepline for all the product blocks in the model(additional delay blocks). These delay blocks confuse me with the the actual feedback delay block that used in the "D_Current_Control" and "Q_Current_Control".

1. The main problem is: should I specify the [Target Frequency] for generating the HDL Code? ie. if I don't specify it the whole model match the FOC period (1/50000)s, the unit delay for integrator works fine. However, if I specify it say 100Mhz, I can put a 100MHz clk in verilog to drive the generated code but I need to carefully encounter how many ceouts(latency) are counted since enable signal is set. And obviously, with these setting the unit delay for integrator part will following the 100MHz clock instead of the FOC 50KHz clock.
2. For generating pratical HDL code, specifically for FOC, should I design the FOC under the base clock frequency 100MHz in verilog (which is the method I am working on), or am I going into the wrong direction?

[Kiran Kintali]

As the model is single rate user can set target clk frequency as 100MHz and then set oversampling factor to 2000 so the generated HDL code gets a clock enable at 50KHz allowing the model to still run at 50KHz with a target frequency of 100MHz

Setting target frequency of 100MHz and Oversampling of 2000 creates a timing controller that takes care of running FOC at desired frequency of 50 KHz,

You can look at the timing controller code that gets generated based on the Target frequency and oversampling setting.

(some useful references on these topics)

• Guidelines for Clock and Reset Signals (Guidelines for specifying Sample Time in Simulink model)to the user to get more insights to such use cases
• Oversampling factor (mathworks.com) (Describes Oversampling Factor and its dependency on clock rate)
• Generate a Global Oversampling Clock (mathworks.com) (Oversampling clock and Oversampling Factor, related information)
• Clocking and Multirate Design (mathworks.com) (Category page with some relevant links to clock rate and Oversampling Factor under ‘Model Settings’)
• Increase Clock Frequency Using Clock-Rate Pipelining - MATLAB & Simulink (mathworks.com)
• Target Frequency Parameter (mathworks.com)