- Please note that subsystem model test harnesses do not support SIL verification, as stated in the following documentation: https://www.mathworks.com/help/releases/R2023b/sltest/ug/select-test-harness-properties-for-your-task.html#bun8a9w
- Kindly refer to the following documentation that specifes the workflow to perform SIL unit tests on atomic subsystems: https://www.mathworks.com/help/releases/R2023b/ecoder/ug/unit-test-subsystem-code-with-silpil-manager.html
- Target-specific (NXP, in this case) custom-code in the model that is not portable for execution on the development computer can lead to build errors. You can refer to the following documentation for SIL simulations to understand more about the limitations for SIL: https://www.mathworks.com/help/releases/R2023b/ecoder/ug/sil-and-pil-simulation-limitations.html#mw_0756ee83-0e45-469c-964a-c60354c06971
- The hardware implementation settings should be configured to allow for SIL compilation on the development computer, as specified in the following documentation: https://www.mathworks.com/help/releases/R2023b/ecoder/ug/software-and-processor-in-the-loop-sil-and-pil-simulation.html#d126e253047
SIL Testing Issue with NXP S32K3xx Hardware Board
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Hello,
I have encountering an issue while attempting to create a SIL test harness for a model using the NXP S32K3xx hardware board. The error message "Error: The model is configured to create a SIL block, which is not supported for the selected hardware board. To resolve this, search for 'Create block' in the Configuration Parameters dialog box and set it to 'None' or 'PIL'" persists, even though the 'Create block' setting is already set to 'None'.
Model and Hardware Configuration Details:
- Hardware Board: NXP S32K3xx
Steps Taken to Troubleshoot:
- Verified 'Create Block' Setting: Double-checked the 'Configuration Parameters' dialog box to ensure that the 'Create block' setting is indeed set to 'None'.
Tried this but still getting the same error.
i have attached an image of configuration parameter of our model and the error message for reference.
1 commentaire
Sumukh
le 24 Déc 2024
Modifié(e) : Sumukh
le 24 Déc 2024
Can you please provide the complete model being used here?
You can refer to the following points to try to identify the issue:
Réponses (1)
Kautuk Raj
le 31 Déc 2024
I can recognize that you are facing an issue with creating a SIL test harness for the NXP S32K3xx hardware board.
When creating a traditional SIL subsystem type harness, you follow the steps below:
- Open any model, for example, "test.slx".
- Right-click the subsystem to create a Test Harness.
- Select the Verification Mode to "Software-in-the-Loop (SIL)" and press OK. Simulink Test sets the "CreateSILPILBlock" parameter to "SIL" and calls slbuild on the subsystem.
The modern approach for SIL/PIL testing of atomic subsystems (where code can be configured to be reusable/nonreusable) is to create a harness in Normal mode, generate top model code, and switch the Simulation mode using either the SIL/PIL manager or Simulink Test Manager.
For more details, you can refer to the following MathWorks documentation: https://www.mathworks.com/help/releases/R2023b/ecoder/ug/unit-test-subsystem-code-with-silpil-manager.html
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