Configuration in FPGA (RFSoC) while implementing WLAN HDL transmitter and receiver modules

Dear all,

I am using the WLAN HDL transmitter and receiver modules generated by matlab, and trying to implement the HDL in Xilinx RFSoC (4x2).

There are some questions about the understanding on WLAN "20 MHz" or "40 MHz".

Here are the webpages: transmitter, receiver.

I also referred to this page for RFDC configuration, which the page is using 40 MHz as example.

But I cannot fully understand the meaning of "20 MHz" or "40 MHz". I would appreciate if anyone can help to explain.

1) First of all, in the HDL modules:

• transmitter HDL module generates a new set of I/Q data (32 bits for each) in every 16 clock-cycles.
• receiver HDL module processes a new set of I/Q data (16 bits for each) in every 8 clock-cycles.

2) Next, in the RFDC configuration from this page with 40 MHz:

• 2560 Msps
• decimation/interpolation: 8
• Samples per clock cycle: 8
• Stream data width: 128 (= 16*8, so 16 bit for each of I/Q?)
• Frequency: 40 MHz (25 ns)

In this configuration, in each clock-cycle of 40 MHz (25 ns), there are 8 sets of I/Q data.

Here the "8 sets of I/Q data in each clock-cycle" are the same? or they are all different 8 data sets?

I am asking this bacause of the consideration on 1).

If 8 data sets in 25 ns are all newly udpate (different), the real data rate is 40 MHz * 8 = 320 MHz.

Then, the transmitter HDL module needs a 16x faster clock to process it, so it will be 320 MHz * 16 = 5.12 GHz.

Similarly, the receiver HDL module needs a 8x faster clock: 320 MHz * 8 = 2.56 GHz.

For both the transmitter and receiver HDL module, they are HDL/RTL to be implemented in FPGA PL. Using a clock of O(GHz) in PL seems to be too fast based on experience.

Is my understanding on the clock rate correct?

Thank you in advance.

Answer 1

[Kranti Balaga]

Consider that clocks and sample rates are two different entities. The PL (Programmable Logic) clocks typically operate in the MHz range. For data rates in the Gsps range, we use frame-based processing, i.e., multiple samples are processed in a single clock cycle.

For example, if 8 samples are processed per clock using a vector interpolator operating at 40 MHz, the effective data rate becomes 8 × 40 = 320 Msps (mega-samples per second), not 320 MHz. Similarly, wherever high data rates are required in the PL (FPGA), we use frame-based processing to meet the performance demands. Therefore, it's appropriate to express data rates in Gsps, not GHz.

As mentioned earlier, in the WLAN SoC model, we used a LUT-based approach, and the RFDC (RF Data Converter) settings were configured accordingly. When integrating the HDL Transmitter, you may need to update the RFDC settings. Specifically, set the DUT clock to the highest available value, ensuring that it reflects the desired stream clock frequency.

I am not sure about "TX HDL module generates a new I/Q sample in every 16 clock-cycles" and "RX HDL module processes a new I/Q sample in every 8 clock-cycles."

TX HDL module output is 20 MHz always. However, there 3 rate changes (160-bit process, 320-after 1/2 rate encoder and 20- Symbol modulator output) inside the transmitter logic.

You cannot directly integrate the HDL Transmitter into the SoC model without modifications. You may need to adjust the interpolation and decimation filters based on the required data rates. For further assistance, please reach out to the appropriate sales representative to establish the proper channel for discussing your use cases and receiving support from our team.

Thanks,

Kranti

[Yun-Tsung]

Thank you. I understood that the HDL design cannot be directly intergrated into the data stream within the RFSoC Vivado project. Some manual adaptation is required.

Answer 2

[Kranti Balaga]

Hi Yun,

Firstly, the SoC example you referred to doesn't include the transmitter model that we shipped in the recent R24b release. However, we used a LUT-based transmitter to verify the WLAN receiver, you can observe this in the example. Regarding the HDL modules, the current transmitter supports only a 20 MHz channel bandwidth.

RFDC configuration, whatever you said is right. But, The data runs at a sample rate of 320 MSPS, which we achieve by decimating or interpolating by a factor of 8. This means we accept or output 8 samples per clock cycle. Therefore, the effective sample rate is 320 MSPS, while the clock rate is 40 MHz, this is the stream clock for the baseband transceiver.

Thanks,

Kranti

[Yun-Tsung]

Thank you for the reply. Here let me explain my question more in detail.

I know that 320 Msps with 8 sample per clock cycle means:

• 8 samples per 25 ns (40 MHz)
• 1 sample per 3.125 ns (320 MHz)

So each one new I/Q sample will be transmitted/received in 3.125 ns (320 MHz). This part is no problem to me.

My question is, connecting this fact together with the HDL modules (which I would like to implement in RFSoC's FPGA PL).

Based on the behaviors of the HDL modules' design:

• TX HDL module generates a new I/Q sample in every 16 clock-cycles.
• RX HDL module processes a new I/Q sample in every 8 clock-cycles.

If we would like to keep load balance between the HDL modules and the RFDC, we should use:

• TX clock: 320 MHz * 16 = 5.12 GHz.
• RX clock: 320 MHz * 8 = 2.56 GHz.

Is my understanding correct?

[Yun-Tsung]

Let me put a pdf file for better explanation.

My question is mainly about the HDL modules' design (transmitter, receiver) because they takes requires many clock-cycles to process one I/Q data sample with dead time, so a very fast clock is needed. But clock > 1 GHz is basically not impossible in FPGA PL.