How to get my FIL simulation to run faster than pure Simulink

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I would like to see a speed performance increase when I off-load some computation in my model to my FPGA using FPGA-in-the-loop simulation. To start I am using the following example model "Algorithm Verification with a FIL Source Block".
I worked through the example. At the end of the example, in the section labeled "Results", the example ask you to generate two separate models; one that is just FIL and one that is just plain Simulink. Then you compare the time it takes to simulate each using tic and toc. I did this by doing "Save As" on the model to spawn two copies of the example model 'fil_sobel' into "fil_sobel_model_1" and "fil_sobel_model_2", then deleted the FIL parts from "fil_sobel_model_1" and deleted the plain Simulink parts from " "fil_sobel_model_2". 
We then timed the simulation time and got the following results.
>> tic; sim('fil_sobel_model_1'); toc
Elapsed time is 1.582517 seconds.
>> tic; sim('fil_sobel_model_2'); toc
Elapsed time is 3.648051 seconds.
The documentation for this example explicitly says that the FIL simulation should run faster but for me that does not seem to be the case. Why is this?

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MathWorks Support Team
MathWorks Support Team le 2 Sep 2021
Modifié(e) : MathWorks Support Team le 27 Sep 2021
Are you using JTAG communication for your FIL simulation? To see a performance improvement we recommend performing FIL simulation with Ethernet transport. We would also recommend using boards that have GMII or SGMII PHY interface. If speed is crucial, there is the PCIe FIL option which is much faster than the Ethernet option. In general for FIL, PCIe is faster than Ethernet which will be faster than JTAG.

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