hdl coder ram usage and source optimizaion

3 vues (au cours des 30 derniers jours)
Fahri Gürbüz
Fahri Gürbüz le 7 Juil 2020
Dear all,
I am using hdl coder and modelling current and speed PI with space vector PWM and SPI blocks. When I go to vivado, I have observed that sources of my fpga is not enough. I am using RAM and memory in order to register data. I am wondering if memory and RAM blocks are using distriuted RAM. If they are using distributed one, then how can I use block ram? In addition, how can I optimize my model so as to reduce source usage?
Regards

Réponse acceptée

Kiran Kintali
Kiran Kintali le 1 Nov 2020
Refer to Block RAM mapping guidelines in this HDL Coder eval reference document.
Getting Started with RAM and ROM in Simulink
web(fullfile(docroot, 'hdlcoder/ug/getting-started-with-ram-and-rom-in-simulink.html'))
Here are some other resources about RAM/ROM Mapping in MATLAB and Simulink to HDL code generation using HDL Coder
web(fullfile(docroot, 'hdlcoder/ug/appropriate-usage-of-delay-blocks-as-registers.html'))
web(fullfile(docroot, 'hdlcoder/ug/generate-fpga-block-ram-lookup-tables.html'))
web(fullfile(docroot, 'hdlcoder/ref/hdl.ram-system-object.html'))
web(fullfile(docroot, 'hdlcoder/ug/persistent-variables-1.html'))
web(fullfile(docroot, 'hdlcoder/ug/model-state-with-persistent-variables-and-system-objects.html'))
web(fullfile(docroot, 'hdlcoder/ug/map-matrices-to-block-rams-to-reduce-area.html'))
web(fullfile(docroot, 'hdlcoder/ug/how-to-map-persistent-arrays-to-ram.html'))
web(fullfile(docroot, 'hdlcoder/ug/appropriate-usage-of-delay-blocks-as-registers.html'))
Please share a sample model for specific guidance to your usecase.

Plus de réponses (0)

Produits

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by