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Question
How to change folder for "slprj" folder generation?
Dear all, I have read the following question https://www.mathworks.com/matlabcentral/answers/535769-how-can-i-change-the-loca...
7 mois il y a | 1 réponse | 0
1
réponseQuestion
How to configure host interface and setup scripts for FPGA I/O?
Dear all, I am making a design for an RFSoC device using SoC Blockset add-on. I have deployed the design, now I want to sa...
8 mois il y a | 1 réponse | 0
1
réponseHow to map logic to RAMs instead of LUTs on FPGA?
Dear all, The solution is as follows: 1) Adjust the function so that it contains 32 smaller vectors from which I access only o...
8 mois il y a | 0
| A accepté
Question
How to map logic to RAMs instead of LUTs on FPGA?
Dear all, I am using SoC Blockset to design an application for an AMD Zynq Ultrascale+ ZCU111 evaluation board. During the...
8 mois il y a | 1 réponse | 0
1
réponseHow to uninstall a support package after deletion of its files?
Hello again! I have contacted MATLAB support for the solution, and here it is: This is a known problem. To re-install the su...
8 mois il y a | 1
| A accepté
Question
How is SoC Blockset working with Cortex-R5 processor on ZCU111?
Dear all, I am using SoC Blockset to design applications for AMD Zynq Ultrascale+ ZCU111 evaulation board, which has a hardwa...
8 mois il y a | 1 réponse | 0
1
réponseQuestion
Where is the algebraic loop coming from?
Dear all, I faced an issue with algebraic loop in simulink (see the model attached). When I update the model it says "Algebr...
9 mois il y a | 2 réponses | 0
2
réponsesQuestion
How to uninstall a support package after deletion of its files?
Dear all, I am using MATLAB on Linux, where the support packages (add-ons for HW support) are installed under the "/home/<user...
9 mois il y a | 2 réponses | 0
2
réponsesQuestion
How to send data from an RFSoC device to the Host PC?
Dear all, I am using AMD Zynq Ultrascale+ ZCU111 evaluation board for a simple receiver design. Currently I record a signal fr...
10 mois il y a | 1 réponse | 0
1
réponseHow to make a proper data transfer between FPGA and Processor?
The issue can be resolved as this: The samples, produced by the FPGA algorithm, are added to a FIFO in packages of N samples, f...
11 mois il y a | 0
| A accepté
Question
How to make a proper data transfer between FPGA and Processor?
Dear all, I am using SoC Blockset for a simple receiver design for ZCU111 board. ADC is producing samples with period Ts,...
11 mois il y a | 2 réponses | 0
2
réponsesQuestion
How are RFDC block and AXI4-Stream to Software block settings applied to the target board by SoC Builder?
Dear all, I am using SoC Blockset for a simple receiver design for AMD Zynq Ultrascale+ ZCU111 evaluation board. The Top mod...
12 mois il y a | 1 réponse | 0
1
réponseQuestion
Spectrum block shows incorrect dbm value
Dear all, In the attached model NCO generates a sine wave of 32MHz and spectrum is set to RBW of 1MHz, 50Ohm resistance. We ...
12 mois il y a | 1 réponse | 0
1
réponseQuestion
Does SoC Builder do build optimizations, can I see the resources mapping and can I change it?
Dear all, I am using SoC Blockset for a simple design for AMD Zynq Ultrascale+ ZCU111 evaluation board. If I understand it...
12 mois il y a | 2 réponses | 0
2
réponsesQuestion
Propagation of signals in RF Data Converter block in simulation and on hardware
Dear all, I am using SoC Blockset to design a simple receiver using AMD Zynq Ultrascale+ ZCU111 evaluation board. The relevan...
environ un an il y a | 1 réponse | 0
1
réponseQuestion
RF Data Converter: input/output data types
Dear all, I am using the SoC Blockset add-on to create a design for ZCU111 evaluation board. 1) The RF Data converter bloc...
environ un an il y a | 1 réponse | 0
1
réponseStep wise execution of "Transmit and Receive Tone Using AMD RFSoC Device" for ZCU208 RFSoC Board
The step-by-step explanation would be too conprehensive not only for explaining, but for reading also. The best thing to do is t...
environ un an il y a | 0
Question
AXI4-Stream to Software clock frequency does not match FPGA clock frequency
Dear all, I am using SoC Blockset add-on and checking out the example "Transmit and Receive Tone Using RFSoC Device" (https://w...
environ un an il y a | 1 réponse | 0
1
réponseQuestion
Help to understand RF Data Converter clocking
Dear all, I am starting to use SoC Blockset add-on and now figuring out how RF Data Converter block works. For example I set...
environ un an il y a | 1 réponse | 0
1
réponseQuestion
Cannot find SoCData and rteEvent datatypes characteristics
Dear all, I was trying to figure out the following about SoCData datatype: 1) What are its dimensions? 2) Is this real or ...
environ un an il y a | 2 réponses | 0
2
réponsesQuestion
Why do we need Asynchronous Task Specification block?
Dear all, I am learning how to work with SoC Blockset and curious about why we need Asynchronous Task Specification in Event-...
environ un an il y a | 1 réponse | 0
1
réponseQuestion
Data types mismatch in Simulink
Dear all, in the attached file you can find a project, obtained by following the instructions in SoC Blockset User's Guide, ...
environ un an il y a | 1 réponse | 0
1
réponseQuestion
Not possible to set-up SoC Blockset Support Package for AMD FPGA and SoC Devices
Dear all, I am using ZCU111 directly connected to PC with Ethernet cable and trying to install SoC Blockset Support Package fo...
environ un an il y a | 1 réponse | 0
