Version 5.3, part of Release 2017b, includes the following enhancements:

  • SystemVerilog DPI Custom Port Widths: Generate SystemVerilog ports with bit widths that match non-byte-aligned fixed-point widths​
  • Additional FPGA-in-the-Loop Board Support: Simulate with Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

See the Release Notes for details.

Version 5.2, part of Release 2017a, includes the following enhancements:

  • FPGA Data Capture: Probe internal FPGA signals to analyze in MATLAB or Simulink
  • HDL Code Coverage: Activate HDL simulator code coverage in generated test benches
  • MATLAB Based AXI Master: Interactively read and write AXI4 and AXI4-Lite signals on your FPGA​
  • SystemVerilog DPI Test Bench Generation: Speed up test bench generation from Simulink models with large data sets​
  • Native Floating-Point Test Bench: Generate SystemVerilog DPI, cosimulation, and FPGA-in-the-loop test benches that have single-precision data types (requires HDL Coder)

See the Release Notes for details.

Version 5.1, part of Release 2016b, includes the following enhancements:

  • FPGA Data Capture: Probe internal FPGA signals to analyze in MATLAB or Simulink
  • FPGA-in-the-Loop for Control Applications: Return a larger output data size when using an overclocking factor
  • FPGA-in-the-Loop Custom Clock Speed: Specify the FPGA system clock frequency in the FIL Wizard
  • Multirate SystemVerilog DPI Components: Generate multirate test benches to verify that your generated component matches Simulink behavior
  • Logic Analyzer: Visualize, measure, and analyze transitions and states over time for Simulink signals (requires DSP System Toolbox)

See the Release Notes for details.

Version 5.0, part of Release 2016a, includes the following enhancements:

  • PCI Express FPGA-in-the-Loop: Perform FIL simulation on selected Xilinx and Intel development boards
  • Faster Test Bench Generation and HDL Simulation: Generate SystemVerilog DPI test benches for large data sets from HDL Coder
  • Expanded Data Type Support in SystemVerilog DPI: Generate SystemVerilog DPI components for models that have buses, structures, or complex signals as I/O
  • Additional FPGA Board Support: Perform FPGA-in-the-loop simulation with Xilinx Kintex UltraScale and Intel MAX 10 family boards

See the Release Notes for details.

Version 4.7, part of Release 2015b, includes the following enhancements:

See the Release Notes for details.