Generate Native Floating-Point FPGA Implementations for Field-Oriented Control of Motors

FPGA and ASIC hardware is a fixed set of resources. Typically, the most efficient way to configure a Simulink^® model to run on target hardware is to convert the data types and arithmetic operations to use fixed-point types. Fixed-Point Designer™ automates and manages this process. But some designs and operations require a high-dynamic range, making it difficult to find an efficient fixed-point implementation. HDL Coder™ now supports native floating-point code generation, where you can implement your high-dynamic range operations in single-precision floating point, and generate VHDL or Verilog^® code directly without converting to fixed-point types and operations.