Use Target Hardware Instruction Set Extensions to Generate SIMD Code from Simulink Blocks for Intel Platforms

Note

This workflow requires a Simulink^® Coder™ license or an Embedded Coder^® license.

This topic shows how to generate SIMD code from Simulink blocks using the model configuration parameter Leverage target hardware instruction set extensions. To generate SIMD code using the Intel^® AVX2 code replacement library, see Use Intel AVX2 Code Replacement Library to Generate SIMD Code from Simulink Blocks. The code replacement library also applies other optimizations, whereas the configuration parameter applies only SIMD optimizations.

1. Open the Simulink Coder app or the Embedded Coder app from the Apps gallery in the Simulink model toolstrip.

2. In the C Code tab that opens, click Settings > Hardware Implementation.

3. Set the Device vendor (Simulink) parameter to Intel or AMD.

4. Set the Device type (Simulink) parameter to x86-64(Windows 64) or x86-64(Linux 64).

5. On the Code Generation > Optimization pane, for the Leverage target hardware instruction set extensions (Simulink Coder) parameter, select the instruction set extension supported by your processor. For this example, select SSE2. If you use Embedded Coder, you can also select from the instruction sets SSE, SSE4.1, AVX, AVX2, FMA, and AVX512F.

6. Select the Optimize reductions (Simulink Coder) parameter to generate SIMD code for reduction operations.

7. On the Code Generation > Interface pane, under Software environment, set Code replacement libraries to None, and clear Support non-finite numbers.

8. Depending on the blocks you have used in your model, you might have to change additional block-level settings to generate SIMD code using this workflow. For more information on these settings, see the Extended Capabilities > C/C++ Code Generation sections in the respective block reference pages.

9. Generate code from the model.

The SIMD instructions are the intrinsic functions that start with the identifier _mm in the generated code. These functions process multiple data in a single iteration of the loop because the loop increments by four for single data types and by two for double data types. For models that process more data and are computationally more intensive, the SIMD instructions can significantly speed up the code execution time.

Related Topics

• Simulink Blocks in DSP System Toolbox that Support SIMD Code Generation
• Use Target Hardware Instruction Set Extensions to Generate SIMD Code from Simulink Blocks for ARM Cortex-A Processors
• Use Intel AVX2 Code Replacement Library to Generate SIMD Code from Simulink Blocks
• Use Intel AVX2 Code Replacement Library to Generate SIMD Code from MATLAB Algorithms
• Optimize Code for Reduction Operations by Using SIMD (Simulink Coder)
• Generate SIMD Code from Simulink Blocks for Intel Platforms (Simulink Coder)
• Generate Code Using Embedded Coder (Embedded Coder)