General CRC Syndrome Detector

Detect errors in received codeword frames according to generator polynomial

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Libraries:
Communications Toolbox / Error Detection and Correction / CRC

Description

The General CRC Syndrome Detector block computes cyclic redundancy check (CRC) checksums for received codeword frames. For successful CRC detection in a communications system link, you must align the parameter settings of the General CRC Syndrome Detector block with the paired General CRC Generator block.

For more information, see CRC Syndrome Detector Operation.

Examples

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Use a CRC code to detect frame errors in a noisy BPSK signal.

In the cm_ex_crc_noisy_bpsk_frames model, the CRC generator and detector pair use a standard CRC-4 polynomial, . The length of the CRC is 4 bits as determined by the degree of the polynomial. The number of checksums per frame is 1, so the full transmission frame has one CRC appended at the end.

A binary signal frame gets a CRC code appended to the end of the frame. BPSK modulation is applied to the signal and the signal passes through an AWGN channel. The signal is demodulated, and then a CRC syndrome detector removes the CRC and calculates the CRC errors.

Generate 12-bit frames of binary data and append CRC bits. Based on the degree of the polynomial, 4 bits are appended to each frame. Apply BPSK modulation and pass the signal through an AWGN channel. Demodulate and use the CRC detector to determine if the frame is in error.

The results of the CRC detection are compared to a BER calculation.

Number of bit errors detected:  6
Number of crc errors detected:  7

Ports

Input

In — Received codeword

binary column vector

Received codeword, specified as a binary column vector.

Data Types: double | Boolean

Output

Out — Output frame

binary column vector

Output frame, returned as a binary column vector that inherits the data type of the input signal. The output frame contains the received codeword with the checksums removed.

The length of the output frame is n - k * r bits, where n is the size of the received codeword, k is the number of checksums per frame, and r is the degree of the generator polynomial.

Err — Checksum error signal

binary column vector

Checksum error signal, returned as a binary column vector that inherits the data type of the input signal. The length of Err equals the value of Checksums per frame. For each checksum computation, an element value of 0 in Err indicates no checksum error, and an element value of 1 in Err indicates a checksum error.

Parameters

To edit block parameters interactively, use the Property Inspector. From the Simulink^® Toolstrip, on the Simulation tab, in the Prepare gallery, select Property Inspector.

Generator polynomial — Generator polynomial

'z^16 + z^12 + z^5 + 1' (default) | polynomial character vector | binary row vector | integer row vector

Generator polynomial for the CRC algorithm, specified as one of the following:

• A polynomial character vector such as 'z^3 + z^2 + 1'.

• A binary row vector that represents the coefficients of the generator polynomial in order of descending power. The length of this vector is (N+1), where N is the degree of the generator polynomial. For example, [1 1 0 1] represents the polynomial x³+ z²+ 1.

• An integer row vector containing the exponents of z for the nonzero terms in the polynomial in descending order. For example, [3 2 0] represents the polynomial z³ + z² + 1.

For more information, see Representation of Polynomials in Communications Toolbox.

Some commonly used generator polynomials include:

CRC method	Generator polynomial
CRC-32	'z^32 + z^26 + z^23 + z^22 + z^16 + z^12 + z^11 + z^10 + z^8 + z^7 + z^5 + z^4 + z^2 + z + 1'
CRC-24	'z^24 + z^23 + z^14 + z^12 + z^8 + 1'
CRC-16	'z^16 + z^15 + z^2 + 1'
Reversed CRC-16	'z^16 + z^14 + z + 1'
CRC-8	'z^8 + z^7 + z^6 + z^4 + z^2 + 1'
CRC-4	'z^4 + z^3 + z^2 + z + 1'

Example: 'z^7 + z^2 + 1', [1 0 0 0 0 1 0 1], and [7 2 0] represent the same polynomial, p(z) = z ⁷ + z ² + 1.

Initial states — Initial states of internal shift register

0 (default) | 1 | binary row vector

Initial states of the internal shift register, specified as a binary scalar or a binary row vector with a length equal to the degree of the generator polynomial. A scalar value is expanded to a row vector of equal length to the degree of the generator polynomial.

Direct method — Use direct algorithm for CRC checksum calculations

off (default) | on

Select to use the direct algorithm for CRC checksum calculations. When cleared, the block uses the non-direct algorithm for CRC checksum calculations.

For more information on direct and non-direct algorithms, see Error Detection and Correction.

Reflect input bytes — Reflect input bytes

off (default) | on

Select to flip the received codeword on a bytewise basis before entering the data into the shift register. When Reflect input bytes is selected, the received codeword length divided by the value of the Checksums per frame parameter must be an integer and a multiple of 8. When Reflect input bytes is cleared, the block does not flip the input data.

Reflect checksums before final XOR — Reflect checksums before final XOR

off (default) | on

Select Reflect checksums before final XOR to flip the CRC checksums around their centers after the input data are completely through the shift register. When Reflect checksums before final XOR is cleared, the block does not flip the CRC checksums.

Final XOR — Final XOR

0 (default) | 1 | binary row vector

Final XOR, specified as a binary scalar or a binary row vector with a length equal to the degree of the generator polynomial. The XOR operation runs using the value of the Final XOR parameter and the CRC checksum before comparing with the input checksum. A scalar value is expanded to a row vector of equal length to the degree of the generator polynomial. A setting of 0 is equivalent to no XOR operation.

Checksums per frame — Number of checksums calculated for each frame

1 (default) | positive integer

Number of checksums calculated for each frame, specified as a positive integer.

Block Characteristics

Data Types	Boolean | double
Multidimensional Signals	no
Variable-Size Signals	yes

More About

Cyclic Redundancy Check Coding

Cyclic redundancy check (CRC) coding is an error-control coding technique for detecting errors that occur when a data frame is transmitted. Unlike block or convolutional codes, CRC codes do not have a built-in error-correction capability. Instead, when a communications system detects an error in a received codeword, the receiver requests the sender to retransmit the codeword.

In CRC coding, the transmitter applies a rule to each data frame to create extra CRC bits, called the checksum or syndrome, and then appends the checksum to the data frame. After receiving a transmitted codeword, the receiver applies the same rule to the received codeword. If the resulting checksum is nonzero, an error has occurred and the transmitter should resend the data frame.

When the number of checksums per frame is greater than 1, the input data frame is divided into subframes, the rule is applied to each data subframe, and individual checksums are appended to each subframe. The subframe codewords are concatenated to output one frame.

For a discussion of the supported CRC algorithms, see Cyclic Redundancy Check Codes.

CRC Syndrome Detector Operation

The CRC syndrome detector outputs the received message frame and a checksum error vector according to the specified generator polynomial and number of checksums per frame.

The checksum bits are removed from each subframe, so that the resulting the output frame length is n - k × r, where n is the size of the received codeword, k is the number of checksums per frame, and r is the degree of the generator polynomial. The input frame must be evenly divisible by k.

For a specific initial state of the internal shift register:

1. The received codeword is divided into k equal sized subframes.

2. The CRC is removed from each of the k subframes and compared to the checksum calculated on the received codeword subframes.

3. The output frame is assembled by concatenating the subframe bits of the k subframes and then output as a column vector.

4. The checksum error is output as a binary column vector of length k. An element value of 0 indicates an error-free received subframe, and an element value of 1 indicates an error occurred in the received subframe.

For the scenario shown here, a 16-bit codeword is received, a third degree generator polynomial computes the CRC checksum, the initial state is 0, and the number of checksums per frame is 2.

Since the number of checksums per frame is 2 and the generator polynomial degree is 3, the received codeword is split in half and two checksums of size 3 are computed, one for each half of the received codeword. The initial states are not shown, because an initial state of [0] does not affect the output of the CRC algorithm. The output frame contains the concatenation of the two halves of the received codeword as a single vector of size 10. The checksum error signal output contains a 2-by-1 binary frame vector whose entries depend on whether the computed checksums are zero. As shown in the figure, the first checksum is nonzero and the second checksum is zero, indicating an error occurred in reception of the first half of the codeword.

References

[1] Sklar, Bernard. Digital Communications: Fundamentals and Applications. Englewood Cliffs, N.J.: Prentice-Hall, 1988.

[2] Wicker, Stephen B. Error Control Systems for Digital Communication and Storage. Upper Saddle River, N.J.: Prentice Hall, 1995.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced before R2006a