Integer-Output RS Decoder HDL Optimized

Decode data using Reed-Solomon (RS) decoder

• Library:

• Communications Toolbox HDL Support / Error Detection and Correction / Block

  Communications Toolbox / Error Detection and Correction / Block

• 

Description

The Integer-Output RS Decoder HDL Optimized decodes data using RS decoder. The RS decoding follows the same standards as any other cyclic redundancy code. Use this block to model communications system forward error correction (FEC) codes.

For more information about the RS decoder, see the Integer-Output RS Decoder block. For more information on representing data for RS codes, see Integer Format (Reed-Solomon Only).

Ports

Input

dataIn — Input data

scalar

Input data, specified as a scalar representing one symbol. For binary point scaling, the input data type must be an integer or fixdt. The double data type is allowed for simulation, but not for HDL code generation.

Data Types: double | int8 | int16 | int32 | int64 | fixed point

startIn — Start of input frame indicator

scalar

Start of input frame indicator, specified as a Boolean scalar.

Data Types: Boolean

endIn — End of input frame indicator

scalar

End of input frame indicator, specified as a Boolean scalar.

Data Types: Boolean

validIn — Valid input data indicator

scalar

Valid input data indicator, specified as a Boolean scalar.

This is a control signal that indicates if the data on the dataIn port is valid.

Data Types: Boolean

Output

dataOut — Decoded message data

scalar

Decoded message data, returned as a scalar. This output data width is the same size as the input data.

Data Types: double | int8 | int16 | int32 | int64 | fixed point

startOut — Start of output frame indicator

scalar

Start of output frame indicator, returned as a Boolean scalar.

Data Types: Boolean

endOut — End of output frame indicator

scalar

End of output frame indicator, returned as a Boolean scalar.

Data Types: Boolean

validOut — Valid output data indicator

scalar

Valid output data indicator, returned as a Boolean scalar.

This is a control signal that indicates if the data on the dataOut port is valid.

Data Types: Boolean

errOut — Indications of corruption of received data

scalar

Indications of corruption of the received data, returned as a Boolean scalar.

Data Types: Boolean

numErrors — Number of detected errors

nonnegative scalar

Number of detected errors, returned as a nonnegative scalar.

Dependencies

To enable this port, select the Output number of corrected symbol errors parameter.

Data Types: uint8

Parameters

Codeword length — Length of codeword

7 (default) | range from 7 to 65, 535

Specify the codeword length.

The codeword length N must be an integer equal to 2^M – 1, where M is an integer in the range from 3 to 16. For more information on representing data for RS codes, see Integer Format (Reed-Solomon Only).

Message length — Length of message

3 (default) | positive integer

Specify the length of the message.

For more information on representing data for RS codes, see Integer Format (Reed-Solomon Only).

Source of primitive polynomial — Primitive polynomial source

Auto (default) | Property

Specify the source of the primitive polynomial.

• Select Auto to specify the primitive polynomial based on the Codeword length (N) parameter value. The degree of the primitive polynomial is calculated as M = ceil(log₂(Codeword length (N)). .

• Select Property to specify the primitive polynomial using the Primitive polynomial parameter.

Primitive polynomial — Primitive polynomial

[ 1 0 1 1 ] (default) | binary row vector

Specify a binary row vector representing the primitive polynomial in descending order of powers.

For more information on how to specify a primitive polynomial, see Primitive Polynomials and Element Representations.

Dependencies

To enable this parameter, set the Source of primitive polynomial parameter to Property.

Source of B, the starting power for roots of the primitive polynomial — Source of starting power for roots of primitive polynomial

Auto (default) | Property

Specify the source of the starting power for roots of the primitive polynomial.

• Select Property to enable the B value parameter.

• Select Auto, to use the B value parameter default value of 1.

B value — Starting exponent of roots

1 (default) | positive integer

The starting exponent of the roots.

Dependencies

To enable this parameter, set the Source of B, the starting power for roots of the primitive polynomial parameter to Property.

Output number of corrected symbol errors — Number of corrected symbol errors

off (default) | on

Select this parameter to enable the numErrors output port. This port outputs the detected symbol error count.

Model Examples

Using HDL Optimized RS Encoder/Decoder Library Blocks

Implement encoder and decoder for the IEEE® 802.16 standard [ 1 ] using the HDL Optimized Reed-Solomon (RS) Encoder and Decoder library blocks.

Algorithms

This figure shows a sample output of the Integer-Output RS Decoder HDL Optimized block with a default configuration.

Troubleshooting

• Each input frame must contain more than (N– K) x 2 symbols and less than or equal to N symbols. A shortened code is inferred when the number of valid data samples between startIn and endIn is less than N. A shortened code still requires N cycles to perform the Chien search. If the input is less than N symbols, leave a guard interval of at least N-size inactive cycles before starting the next frame.

• The decoder can operate on up to four messages at a time. If the block receives the start of a fifth message before completely decoding the first message, the block drops data samples from the first message. To avoid this issue, increase the number of inactive cycles between input messages.

• The generator polynomial is not specified explicitly. However, it is defined by the codeword length, message length, and the B value for the starting exponent of the roots.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Not recommended for production code.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

• You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).