Integer-Output RS Decoder HDL Optimized

Decode data using a Reed-Solomon decoder

Library

Block sublibrary of Error Correction and Detection

Description

Reed-Solomon encoding follows the same standards as any other cyclic redundancy code. The Integer-Output RS Decoder HDL Optimized block can be used to model many communication system Forward Error Correcting (FEC) codes.

For more about the Reed-Solomon decoder, see the Integer-Output RS Decoder block reference. For more information on representing data for Reed-Solomon codes, see Integer Format (Reed-Solomon Only).

Signal Attributes

The Integer-Output RS Decoder HDL Optimized block has four input ports and six output ports (5 required, 1 optional).

Port	Direction	Description	Data Type
dataIn	Input	Message data, one symbol at a time.	Integer or fixdt with any binary point scaling. double is allowed for simulation but not for HDL code generation.
startIn	Input	Indicates the start of a frame of data.	Boolean
endIn	Input	Indicates the end of a frame of data.	Boolean
validIn	Input	Indicates that input data is valid.	Boolean
dataOut	Output	Message data with the checksum appended. The data width is the same as the input data port.	Same as dataIn
startOut	Output	Indicates the start of a frame of data.	Boolean
endOut	Output	Indicates the end of a frame of data, including checksum.	Boolean
validOut	Output	Indicates that output data is valid.	Boolean
errOut	Output	Indicates the corruption of the received data when error is high.	Boolean
numErrors	Output (optional)	Count of detected errors.	uint8

Troubleshooting

• Each input frame must contain more than (N-K)*2 symbols, and fewer than or equal to N symbols. A shortened code is inferred when the number of valid data samples between startIn and endIn is less than N. A shortened code still requires N cycles to perform the Chien search. If the input is less than N symbols, leave a guard interval of at least N-size inactive cycles before starting the next frame.

• The decoder can operate on up to 4 messages at a time. If the block receives the start of a fifth message before completely decoding the first message, the block drops data samples from the first message. To avoid this issue, increase the number of inactive cycles between input messages.

• The generator polynomial is not specified explicitly. However, it is defined by the code word length, the message length, and the B value for the starting exponent of the roots. To get the value of B from a generator polynomial, use the genpoly2b function.

Parameters

Codeword length

The length of the code word in symbols, N, must be equal to 2M-1, where M is the input word length. M can be between 3 and 16 bits.

Message length

The message length in symbols, K. The number of parity symbols, N-K, must be a positive even integer, greater than or equal to the input word length, M.

Source of primitive polynomial

Select Property to enable the Primitive polynomial parameter.

Primitive polynomial

Binary row vector representing the primitive polynomial in descending order of powers. When you provide a primitive polynomial, the number of input bits must be an integer multiple of K times the order of the primitive polynomial instead.

This parameter applies when only when Property is selected for Primitive polynomial.

Source of B, the starting power for roots of the primitive polynomial

Select Property to enable the B value parameter. When you select Auto, the block uses B = 1.

B value

The starting exponent of the roots.

This field is available only when you select Property for Source of B, the starting power for roots of the primitive polynomial. The default is 1.

Enable number of errors output

Check this box to enable the numErrors output port. This port outputs the detected symbol error count.

Algorithm

Timing Diagram

Examples

Using HDL Optimized RS Encoder/Decoder Library Blocks

Pair Block

Integer-Input RS Encoder HDL Optimized

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Not recommended for production code.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

• You cannot generate HDL for this block inside a Resettable Synchronous Subsystem.