Get Started with Deep Learning HDL Toolbox
R2026bDeep Learning HDL Toolbox™ provides functions and tools for prototyping and implementing deep learning networks on FPGAs and SoCs. It provides pre-built bitstreams for running deep learning networks on supported FPGAs and SoCs (with SoC Blockset™ for AMD devices and HDL Coder™ for Altera® devices). Profiling and estimation tools enable you to customize a deep learning network by exploring design, performance, and resource utilization tradeoffs.
You can use the toolbox for customizing the hardware implementation of your deep learning network. Also, you can generate portable, synthesizable Verilog®, SystemVerilog, and VHDL® code for deployment on any FPGA or SoC devices (with HDL Coder and Simulink®).
Tutorials
- Supported Networks, Boards, and Tools
Pretrained deep learning networks and network layers for which code can be generated by Deep Learning HDL Toolbox.
- Supported Layers
Layers supported for code generation by Deep Learning HDL Toolbox.
- Try Deep Learning on FPGA with Only Five Additional Lines of MATLAB Code
Use Deep Learning HDL Toolbox to identify objects on a live webcam with the ResNet-18 pretrained network which has been deployed to a FPGA or SoC board.
- Deep Learning on FPGA Solution
Rapidly prototype custom deep learning networks on FPGA by leveraging the deep learning on FPGA solution.
Featured Examples
Get Started with Deep Learning FPGA Deployment on Xilinx ZCU102 SoC
Create, compile, and deploy a dlhdl.Workflow object that has a handwritten character detection network as the network object by using the AMD Soc Blockset Support Package for AMD FPGA and SoC Devices. Use MATLAB® to retrieve the prediction results from the target device.
Get Started with Deep Learning FPGA Deployment on Xilinx ZC706 SoC
Create, compile, and deploy a handwritten character detection series network to an FPGA and use MATLAB® to retrieve the prediction results.
Get Started with Deep Learning FPGA Deployment on Intel Arria 10 SoC
Create, compile, and deploy a dlhdl.Workflow object that has a handwritten character detection series network object by using the HDL Coder™ Support Package for Intel® FPGA and SoC Devices. Use MATLAB® to retrieve the prediction results from the target device.
Detect Objects Using YOLOv4-tiny Network Deployed to FPGA
Perform object detection using a YOLO v4 tiny network deployed to an FPGA.
Profile Network to Determine Performance Bottlenecks
Identify performance bottlenecks in a deep learning network on an FPGA by using the Profile option of the predict method.
Run Sequence Forecasting on FPGA by Using Deep Learning HDL Toolbox
Create, compile, and deploy a long short-term memory (LSTM) network trained on waveform data by using the AMD SoC Blockset Support Package for AMD FPGA and SoC Devices. Use the deployed network to predict future values by using open-loop and closed-loop forecasting. Use MATLAB® to retrieve the prediction results from the target device.
Custom Deep Learning Processor Generation to Meet Performance Requirements
Create a custom processor configuration and estimate the performance of a pretrained series network. You can then modify parameters of the custom processor configuration and re-estimate the performance. Once you have achieved your performance requirements you can generate a custom bitstream by using the custom processor configuration.
Customize Bitstream Configuration to Meet Resource Use Requirements
Deploy a digit recognition network with a target performance of 500 frames per second (FPS) to a Xilinx® ZCU102 ZU4CG device. The target device resource counts are:
Classify Images on FPGA Using Quantized Neural Network
Use Deep Learning HDL Toolbox™ to deploy a quantized deep convolutional neural network (CNN) to an FPGA. In the example you use the pretrained ResNet-18 CNN to perform transfer learning and quantization. You then deploy the quantized network and use MATLAB® to retrieve the prediction results.
