dlhdl.Processor Class

Namespace: dlhdl

Configure processor object to handle deep learning processor IP core input and output data

Since R2023b

Description

Use objects of the dlhdl.Processor class to manage the input and output data from the deep learning processor IP core.

Creation

hProc = dlhdl.Processor(Network=Network,ProcessorConfig=ProcessorConfig) creates a processor object for the deep learning network, Network, and the processor configuration, ProcessorConfig.

Input Arguments

Network — Deep learning network object

SeriesNetwork object | DAGNetwork object | dlnetwork object | quantize object

Deep learning network object, specified as a SeriesNetwork, DAGNetwork, or dlnetwork object.

Example: Network=resnet18

ProcessorConfig — Processor configuration

dlhdl.ProcessorConfig object

Processor configuration, specified as a dlhdl.ProcessorConfig object.

Example: ProcessorConfig=dlhdl.ProcessorConfig

Methods

Public Methods

getExpectedPaddedInputData	Pad input data for deep learning processor IP core
getInt8ToSingleConversionExponent	Retrieve exponent value for int8-to-single data type conversion
getSingleToInt8ConversionExponent	Retrieve exponent value for single-to-int8 data type conversion
getUnpaddedOutputData	Remove padding from deep learning processor IP core output data

Examples

Create Processor Object to Retrieve Padded Input data and Unpadded Output Data

Create a network with an input layer of size 10-by-10-by-5.

layers = [imageInputLayer([10,10,5],'Normalization','none')
convolution2dLayer(3,5,'Padding','same')
regressionLayer];
layers(2).Weights = ones(3,3,5,5);
layers(2).Bias = ones(1,1,5);
net = assembleNetwork(layers);

Create a processor configuration object and set the convolution thread number as nine.

hPC = dlhdl.ProcessorConfig;
hPC.setModuleProperty('conv','ConvThreadNumber',9);

hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                            ConvThreadNumber: 9
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                     Sigmoid: 'off'
                                   TanhLayer: 'off'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                  SwishLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Create a processor object and a random input array of size 10-by-10-by-5.

hProc = dlhdl.Processor(Network=net,ProcessorConfig=hPC);
im = rand(10,10,5);

hProc = 

  Processor with properties:

            Network: [1×1 SeriesNetwork]
    ProcessorConfig: [1×1 dnnfpga.config.CNN5ProcessorConfig]

Retrieve the padded input data by using the getExpectedPaddedInputData method. The size of the output matrix is 10-by-10-by-8. Reshape output to an 800-by-1 matrix.

output = getExpectedPaddedInputData(hProc,im);
paddedData = dnnfpga.format.convert3DInputToDDRVectorFormatConv4(output, 4);

Retrieve the unpadded output data by using getUnpaddedOutputData. The size of the unpadded output data corresponds to the size of the conv layer, which is 10-by-10-by-5.

outH = getUnpaddedOutputData(hProc,paddedData',1,'conv');

Version History

Introduced in R2023b