setModuleProperty

Class: dlhdl.ProcessorConfig
Namespace: dlhdl

Use the setModuleProperty method to set properties of modules within the dlhdl.ProcessorConfig object

Since R2020b

Syntax

setModuleProperty(processorConfigObject,ModuleName,Name,Value)


Description

The setModuleProperty(processorConfigObject,ModuleName,Name,Value) method sets the properties of the module mentioned in ModuleName by using the values specified as Name,Value pairs.

Input Arguments

processorConfigObject — Processor configuration

dlhdl.ProcessorConfig object

Processor configuration, specified as a dlhdl.ProcessorConfig object.

ModuleName — Name of the module whose parameters are to be set

"conv" | "fc" | "custom" | 'conv' | 'fc' | 'custom' | string | character vector

The dlhdl.ProcessorConfig object module name, specified as a character vector or string.

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example:

conv module parameters

ModuleGeneration — Enable or disable convolution module generation as a part of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the convolution module as a part of the deep learning processor configuration.

Example: 'ModuleGeneration', 'on'

LRNBlockGeneration — Enable or disable local response normalization (LRN) block generation as a part of the convolution module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the LRN block as a part of the convolution module of the deep learning processor configuration.

Example: 'LRNBlockGeneration', 'on'

SegmentationBlockGeneration — Enable or disable segmentation block generation as a part of the convolution module of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the segmentation block as a part of the convolution module of the deep learning processor configuration.

GELUBlockGeneration — Option to enable or disable Gaussian error linear unit (GELU) block

'off' (default) | 'on' | character vector

Option to enable or disable Gaussian error linear unit (GELU) block, specified as a character vector.

ConvThreadNumber — Number of parallel convolution processor kernel threads

16 (default) | 4 | 9 | 16 | 25 | 36 | 64 | 256 | unsigned integer

This parameter is the number of parallel 3-by-3 convolution kernel threads that are a part of the conv module within the dlhdl.ProcessorConfig object.

Example: 'ConvThreadNumber', 64

InputMemorySize — Cache block RAM (BRAM) sizes

[227 227 3] (default) | 3D positive integer array

This parameter is a 3D matrix representing input image size limited by the conv module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'InputMemorySize', [227 227 3]

OutputMemorySize — Cache block RAM (BRAM) sizes

[227 227 3] (default) | 3D positive integer array

This parameter is a 3D matrix representing output image size limited by the conv module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'OutputMemorySize', [227 227 3]

FeatureSizeLimit — Maximum input and output feature size

2048 (default) | positive integer

This parameter is a positive integer representing the maximum input and output feature size as a part of the conv module within the dlhdl.ProcessorConfig object.

Example: 'FeatureSizeLimit', 512

fc module parameters

ModuleGeneration — Enable or disable fully connected module generation as a part of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the fully connected module as a part of the deep learning processor configuration.

Example: 'ModuleGeneration', 'on'

SoftmaxBlockGeneration — Enable or disable Softmax block generation as a part of the fully connected module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the Softmax block as a part of the fully connected module of the deep learning processor configuration. When you set this property to off, the Softmax layer is still implemented in software.

Example: 'SoftmaxBlockGeneration', 'on'

GELUBlockGeneration — Option to enable or disable Gaussian error linear unit (GELU) block

'off (default) | 'on' | character vector

Option to enable or disable Gaussian error linear unit (GELU) block, specified as a character vector.

FCThreadNumber — Number of parallel fully connected (fc) MAC threads

4 (default) | 4 | 8 | 16 | 32 | 64 | unsigned integer

This parameter is the number of parallel fc MAC threads that are a part of the fc module within the dlhdl.ProcessorConfig object.

Example: 'FCThreadNumber', 16

InputMemorySize — Cache block RAM (BRAM) sizes

25088 (default) | unsigned integer

This parameter is an unsigned integer representing cache BRAM size limited by the fc module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'InputMemorySize', 9216

OutputMemorySize — Cache block RAM (BRAM) sizes

4096 (default) | unsigned integer

This parameter is an unsigned integer representing cache BRAM size limited by the fc module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'OutputMemorySize', 4096

custom module properties

ModuleGeneration — Enable or disable adder module generation as a part of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the adder module as a part of the deep learning processor configuration.

Example: 'ModuleGeneration', 'on'

Addition — Enable or disable addition layer generation as a part of the custom module of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the addition layer as a part of the custom module of the deep learning processor configuration.

MishLayer — Enable or disable mish layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on | character vector

Use this parameter to control generation of the mish layer as a part of the custom module of the deep learning processor configuration.

Multiplication — Enable or disable multiplication layer generation as a part of the custom module of the deep learning processor configuration

'on' (default) | 'off' | character vector

Use this parameter to control generation of the multiplication layer as a part of the custom module of the deep learning processor configuration.

Resize2D — Enable or disable resize2d layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the resize2d layer as a part of the custom module of the deep learning processor configuration.

Sigmoid — Enable or disable sigmoid layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the sigmoid layer as a part of the custom module of the deep learning processor configuration.

SwishLayer — Enable or disable swish layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the swish layer as a part of the custom module of the deep learning processor configuration.

TanhLayer — Enable or disable tanh layer generation as a part of the custom module of the deep learning processor configuration

'off' (default) | 'on' | character vector

Use this parameter to control generation of the tanh layer as a part of the custom module of the deep learning processor configuration.

InputMemorySize — Cache block RAM (BRAM) sizes

40 (default) | unsigned integer

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'InputMemorySize', 40

OutputMemorySize — Cache block RAM (BRAM) sizes

120 (default) | unsigned integer

This parameter is an unsigned integer representing cache BRAM size limited by the adder module BRAM size within the dlhdl.ProcessorConfig object.

Example: 'OutputMemorySize', 40

Examples

Set Value for ConvThreadNumber Within dlhdl.ProcessorConfig Object

1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for convThreadNumber.

   hPC = dlhdl.ProcessorConfig;
   hPC.setModuleProperty("conv","ConvThreadNumber",25)
   hPC

2. Once you execute the code, the result is:

   hPC = 
   
                       Processing Module "conv"
                               ModuleGeneration: 'on'
                             LRNBlockGeneration: 'off'
                    SegmentationBlockGeneration: 'on'
                            GELUBlockGeneration: 'off'
                               ConvThreadNumber: 25
                                InputMemorySize: [227 227 3]
                               OutputMemorySize: [227 227 3]
                               FeatureSizeLimit: 2048
   
                         Processing Module "fc"
                               ModuleGeneration: 'on'
                         SoftmaxBlockGeneration: 'off'
                            GELUBlockGeneration: 'off'
                                 FCThreadNumber: 4
                                InputMemorySize: 25088
                               OutputMemorySize: 4096
   
                     Processing Module "custom"
                               ModuleGeneration: 'on'
                                       Addition: 'on'
                                      MishLayer: 'off'
                                 Multiplication: 'on'
                                       Resize2D: 'off'
                                        Sigmoid: 'off'
                                     SwishLayer: 'off'
                                      TanhLayer: 'off'
                                InputMemorySize: 40
                               OutputMemorySize: 120
   
                 Processor Top Level Properties
                                 RunTimeControl: 'register'
                                  RunTimeStatus: 'register'
                             InputStreamControl: 'register'
                            OutputStreamControl: 'register'
                                   SetupControl: 'register'
                              ProcessorDataType: 'single'
                               UseVendorLibrary: 'on'
                        LayerNormalizationBlock: 'off'
   
                        System Level Properties
                                 TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                TargetFrequency: 200
                                  SynthesisTool: 'Xilinx Vivado'
                                ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                        SynthesisToolChipFamily: 'Zynq UltraScale+'
                        SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                       SynthesisToolPackageName: ''
                        SynthesisToolSpeedValue: ''

Set Value for InputMemorySize Within dlhdl.ProcessorConfig Object

1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for InputMemorySize.

   hPC = dlhdl.ProcessorConfig;
   hPC.setModuleProperty("fc","InputMemorySize",25060)
   hPC

2. Once you execute the code, the result is:

   hPC = 
   
                       Processing Module "conv"
                               ModuleGeneration: 'on'
                             LRNBlockGeneration: 'off'
                    SegmentationBlockGeneration: 'on'
                            GELUBlockGeneration: 'off'
                               ConvThreadNumber: 16
                                InputMemorySize: [227 227 3]
                               OutputMemorySize: [227 227 3]
                               FeatureSizeLimit: 2048
   
                         Processing Module "fc"
                               ModuleGeneration: 'on'
                         SoftmaxBlockGeneration: 'off'
                            GELUBlockGeneration: 'off'
                                 FCThreadNumber: 4
                                InputMemorySize: 25060
                               OutputMemorySize: 4096
   
                     Processing Module "custom"
                               ModuleGeneration: 'on'
                                       Addition: 'on'
                                      MishLayer: 'off'
                                 Multiplication: 'on'
                                       Resize2D: 'off'
                                        Sigmoid: 'off'
                                     SwishLayer: 'off'
                                      TanhLayer: 'off'
                                InputMemorySize: 40
                               OutputMemorySize: 120
   
                 Processor Top Level Properties
                                 RunTimeControl: 'register'
                                  RunTimeStatus: 'register'
                             InputStreamControl: 'register'
                            OutputStreamControl: 'register'
                                   SetupControl: 'register'
                              ProcessorDataType: 'single'
                               UseVendorLibrary: 'on'
                        LayerNormalizationBlock: 'off'
   
                        System Level Properties
                                 TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                TargetFrequency: 200
                                  SynthesisTool: 'Xilinx Vivado'
                                ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                        SynthesisToolChipFamily: 'Zynq UltraScale+'
                        SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                       SynthesisToolPackageName: ''
                        SynthesisToolSpeedValue: ''

Set Value for InputMemorySize Within dlhdl.ProcessorConfig Object

1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for InputMemorySize.

   hPC = dlhdl.ProcessorConfig;
   hPC.setModuleProperty("custom","InputMemorySize",80)
   hPC

2. Once you execute the code, the result is:

   hPC = 
   
                       Processing Module "conv"
                               ModuleGeneration: 'on'
                             LRNBlockGeneration: 'off'
                    SegmentationBlockGeneration: 'on'
                            GELUBlockGeneration: 'off'
                               ConvThreadNumber: 16
                                InputMemorySize: [227 227 3]
                               OutputMemorySize: [227 227 3]
                               FeatureSizeLimit: 2048
   
                         Processing Module "fc"
                               ModuleGeneration: 'on'
                         SoftmaxBlockGeneration: 'off'
                            GELUBlockGeneration: 'off'
                                 FCThreadNumber: 4
                                InputMemorySize: 25088
                               OutputMemorySize: 4096
   
                     Processing Module "custom"
                               ModuleGeneration: 'on'
                                       Addition: 'on'
                                      MishLayer: 'off'
                                 Multiplication: 'on'
                                       Resize2D: 'off'
                                        Sigmoid: 'off'
                                     SwishLayer: 'off'
                                      TanhLayer: 'off'
                                InputMemorySize: 80
                               OutputMemorySize: 120
   
                 Processor Top Level Properties
                                 RunTimeControl: 'register'
                                  RunTimeStatus: 'register'
                             InputStreamControl: 'register'
                            OutputStreamControl: 'register'
                                   SetupControl: 'register'
                              ProcessorDataType: 'single'
                               UseVendorLibrary: 'on'
                        LayerNormalizationBlock: 'off'
   
                        System Level Properties
                                 TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                TargetFrequency: 200
                                  SynthesisTool: 'Xilinx Vivado'
                                ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                        SynthesisToolChipFamily: 'Zynq UltraScale+'
                        SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                       SynthesisToolPackageName: ''
                        SynthesisToolSpeedValue: ''

Turn off conv module Within dlhdl.ProcessorConfig Object

1. Create an example object by using the dlhdl.ProcessorConfig class, and then use the setModuleProperty method to set the value for ModuleGeneration.

   hPC = dlhdl.ProcessorConfig;
   hPC.setModuleProperty("conv","ModuleGeneration", "off")
   hPC

2. Once you execute the code, the result is:

   hPC = 
   
                       Processing Module "conv"
                               ModuleGeneration: 'off'
   
                         Processing Module "fc"
                               ModuleGeneration: 'on'
                         SoftmaxBlockGeneration: 'off'
                            GELUBlockGeneration: 'off'
                                 FCThreadNumber: 4
                                InputMemorySize: 25088
                               OutputMemorySize: 4096
   
                     Processing Module "custom"
                               ModuleGeneration: 'on'
                                       Addition: 'on'
                                      MishLayer: 'off'
                                 Multiplication: 'on'
                                       Resize2D: 'off'
                                        Sigmoid: 'off'
                                     SwishLayer: 'off'
                                      TanhLayer: 'off'
                                InputMemorySize: 40
                               OutputMemorySize: 120
   
                 Processor Top Level Properties
                                 RunTimeControl: 'register'
                                  RunTimeStatus: 'register'
                             InputStreamControl: 'register'
                            OutputStreamControl: 'register'
                                   SetupControl: 'register'
                              ProcessorDataType: 'single'
                               UseVendorLibrary: 'on'
                        LayerNormalizationBlock: 'off'
   
                        System Level Properties
                                 TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                                TargetFrequency: 200
                                  SynthesisTool: 'Xilinx Vivado'
                                ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                        SynthesisToolChipFamily: 'Zynq UltraScale+'
                        SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                       SynthesisToolPackageName: ''
                        SynthesisToolSpeedValue: ''

Version History

Introduced in R2020b