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hdlcoder.ReferenceDesign class

Package: hdlcoder

Reference design registration object that describes SoC reference design

Description

refdesign = hdlcoder.ReferenceDesign('SynthesisTool', toolname) creates a reference design object that you use to register a custom reference design for an SoC platform.

To specify the characteristics of your reference design, set the properties of the reference design object.

Use a reference design tool version that is compatible with the supported tool version. If you choose a different tool version, it is possible that HDL Coder™ is unable to create the reference design project for IP core integration.

Construction

refdesign = hdlcoder.ReferenceDesign('SynthesisTool',toolname) creates a reference design object that you use to register a custom reference design for an SoC platform.

Input Arguments

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Synthesis tool name, specified as a character vector.

Example: 'Altera Quartus II'

Properties

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Reference design name, specified as a character vector. In the HDL Workflow Advisor, this name appears in the Reference design drop-down list.

Example: 'Default system (Vivado 2015.4)'

Board associated with this reference design, specified as a character vector.

Example: 'Enclustra Mars ZX3 with PM3 base board'

One or more tool versions that work with this reference design, specified as a cell array of character vectors.

Example: {'2015.4'}

Example: {'13.7','14.0'}

One or more design constraint files, specified as a cell array of character vectors. This property is optional.

Example: {'MarsZX3_PM3.xdc'}

Example: {'MyDesign.qsf'}

One or more relative paths to files or folders that the reference design requires, specified as a cell array of character vectors. This property is optional.

Examples of required files or folders:

  • Existing IP core used in the reference design.

    For example, if the IP core, my_ip_core, is in the reference design folder, set CustomFiles to {'my_ip_core']

  • PS7 definition XML file.

    For example, to include a PS7 definition XML file, ps7_system_prj.xml, in a folder, data, set CustomFiles to {fullfile('data', 'ps7_system_prj.xml')}

  • Folder containing existing IP cores used in the reference design. HDL Coder supports only a specific IP core folder name for each synthesis tool:

    • For Altera® Qsys, IP core files must be in a folder named ip. Set CustomFiles to {'ip'}.

    • For Xilinx® Vivado®, IP core files, or a zip file containing the IP core files, must be in a folder named ipcore. Set CustomFiles to {'ipcore'}.

    • For Xilinx EDK, IP core files must be in a folder named pcores. Set CustomFiles to {'pcores'}.

Note

To add IP modules to the reference design, it is recommended to create an IP repository folder that contains these IP modules, and then use the addIPRepository (HDL Coder) method.

Example: {'my_ip_core'}

Example: {fullfile('data', 'ps7_system_prj.xml')}

Example: {'ip'}

Example: {'ipcore'}

Example: {'pcores'}

Specify the device tree file name. For an example that shows how to use different device tree file names when mapping the DUT ports to different AXI4-Stream channels, see Dynamically Create Master Only or Slave Only or Both Master and Slave Reference Designs (HDL Coder).

Example: 'devicetree_axistream_iio.dtb'

Specify whether you want the parameter Insert JTAG MATLAB as AXI Master (HDL Verifier Required) to be displayed in the Set Target Reference Design task of the HDL Workflow Advisor. By default, this property value is set to true. The parameter is displayed in the Set Target Reference Design task. After you enable this property, to specify whether you want the code generator to insert the JTAG MATLAB as AXI Master IP, use the JTAGMATLABasAXIMasterDefaultValue property. If you do not want the parameter to be displayed, set the property value to false.

This property is optional.

Example: 'false'

Specify whether you want the code generator to insert the JTAG MATLAB as AXI Master IP. The values that you specify are the choices for the Insert JTAG MATLAB as AXI Master (HDL Verifier Required) drop-down in the Set Target Reference Design task of the HDL Workflow Advisor. To specify insertion of the JTAG as AXI Master automatically, before you set this property to on, set the AddJTAGMATLABasAXIMasterParameter property to true.

This property is optional.

Example: 'on'

Specify the IP cache zip file to include in your project. When you run the IP Core Generation workflow in the HDL Workflow Advisor, the code generator extracts this file in the Create Project task. The Build FPGA Bitstream task reuses the IP cache, which accelerates reference design synthesis.

This property is optional.

Example: 'ipcache.zip'

Specify whether you want the code generator to report timing failures in the Build FPGA Bitstream task as warnings or errors. When you run the IP Core Generation workflow in the HDL Workflow Advisor, by default, the code generator reports any timing failures as error. If you have implemented the custom logic to resolve timing failures, you can specify these failures to be reported as warning instead of error. To learn more, see Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows (HDL Coder).

This property is optional.

Example: 'hdlcoder.ReportTiming.Warning'

Specify if the reference design has an existing PS.

Example: 'false'

Enable generation of device tree nodes for an HDL Coder generated IP core, and then insert the nodes into the device tree. To enable the generation of device tree nodes for the IP core, HasProcessingSystem must be set to true.

Do not enable this property if you do not need any additional device tree nodes to be inserted into the registered device tree for the generated IP core.

Example: 'true'

Board resources used by reference design, returned as a structure with the fields:

Reference design resources utilized by FPGA lookup tables (LUTs), specified as a number.

Example: hRD.ResourcesUsed.LogicElements = 100

Reference design resources utilized by FPGA DSP slices, specified as a number.

Example: hRD.ResourcesUsed.DSP = 3

Reference design resources utilized by FPGA board RAM resources, specified as a number.

Example: hRD.ResourcesUsed.RAM = 32000

Methods

registerDeepLearningMemoryAddressSpace Add memory address space to reference design
registerDeepLearningTargetInterfaceAdd and register a target interface
validateReferenceDesignForDeepLearningChecks property values in reference design object
Introduced in R2015a