FPGA Debug

R2026b

HDL Coder™ provides FPGA data capture and AXI manager features for debugging and testing implementations on an FPGA or SoC device from MATLAB^® or Simulink^®.

• FPGA data capture — Observe signals from your FPGA design while the design runs on the FPGA. In the data capture process, you can capture a window of signal data from the FPGA based on your configuration, trigger, and capture settings and return the data to MATLAB or Simulink.

• AXI Manager — Read from and write to on-board memory locations from MATLAB or Simulink.

FPGA Data Capture

You must have an HDL design to perform data capture. There are two FPGA data capture workflows:

• You have an existing HDL design.

  1. Use the FPGA Data Capture Component Generator (SoC Blockset) tool to generate the data capture IP.

  2. Manually integrate the generated IP into your HDL design.

  3. Use the FPGA Data Capture (SoC Blockset) tool or the generated hdlverifier.FPGADataReader (SoC Blockset) System object™ to capture data.

  For an example, see Capture Temperature Sensor Data from AMD FPGA Board Using FPGA Data Capture (SoC Blockset).

• You have a Simulink model and an HDL Coder license.

  1. Use the HDL Workflow Advisor tool to generate the data capture IP and integrate it into the design.

  2. Use the FPGA Data Capture (SoC Blockset) tool or the generated hdlverifier.FPGADataReader (SoC Blockset) System object to capture data.

  For an example, see Debug IP Core Using FPGA Data Capture (SoC Blockset).

For more detailed generation and data capture steps for both workflows, see Data Capture Workflow (SoC Blockset).

Key Capabilities

At run-time, from MATLAB or Simulink, you can:

• Specify trigger conditions that control when to capture the data. See Triggers.

• Specify a sequence of trigger conditions at multiple stages. See Sequential Trigger.

• Specify a capture condition that controls which data to capture. See Capture Conditions.

• Specify data types for the captured data. See Data Type.

• Specify number of windows to capture. See Number of capture windows.

Supported FPGA Vendors and Interfaces

FPGA data capture supports these FPGA vendors and interfaces:

• AMD^®

  • JTAG

  • Ethernet

    • Programmable logic (PL) Ethernet

    • Processing system (PS) Ethernet

  • USB Ethernet

• Intel^®

  • JTAG

For a complete list of supported boards and interfaces, see Supported Third-Party Tools and Hardware (SoC Blockset).

AXI Manager

You must have an HDL design to perform AXI manager operations. There are two AXI manager workflows:

• You have an existing HDL design.

  • For JTAG, PCI Express^®, or PL Ethernet interface — Manually add and integrate the pregenerated AXI manager IP into your HDL design. For an example, see Access FPGA Memory Using JTAG-Based AXI Manager (SoC Blockset).

  • For PS Ethernet or USB Ethernet interface — You need not to include an AXI manager IP in your HDL design. The HDL design directly responds to read and write commands from MATLAB or Simulink.

    For a PS Ethernet interface, follow the setup steps in Ethernet AXI Manager for AMD Zynq SoC Devices (SoC Blockset). For a USB Ethernet interface, follow the setup steps in USB Ethernet AXI Manager (SoC Blockset).

  For more detailed steps for accessing memory-mapped locations with this workflow, see Set Up AXI Manager (SoC Blockset).

• You have MATLAB code or a Simulink model and an HDL Coder license.

  Use the HDL Workflow Advisor tool to add and integrate the AXI manager IP into the design. For examples, see Debug and Control Generated HDL IP Core by using JTAG AXI Manager and Use IP Core Generation to Access DUT Registers on Pure AMD FPGA Devices.

For more detailed steps for accessing memory-mapped locations with this workflow, see Specify Insertion of AXI Manager IP.

Key Capabilities

To read and write memory-mapped locations on the board:

• From MATLAB — Create an aximanager object and use the readmemory and writememory functions.

• From Simulink — Create a Simulink model and include the AXI Manager Read and AXI Manager Write blocks.

Supported FPGA Vendors and Interfaces

AXI manager supports these FPGA vendors and interfaces:

• AMD

  • JTAG

  • Ethernet

    • PL Ethernet

    • PS Ethernet (Not supported via HDL Coder workflow)

  • PCI Express (Not supported via HDL Coder workflow)

  • USB Ethernet (Not supported via HDL Coder workflow)

• Intel

  • JTAG

  • Ethernet

    • PL Ethernet

  • PCI Express (Not supported via HDL Coder workflow)

For a complete list of supported boards and interfaces, see Supported Third-Party Tools and Hardware (SoC Blockset).

Preregistered FPGA Devices with FPGA Debug

Install HDL Coder Support Package for Intel FPGA and SoC Devices

HDL Coder supports FPGA data capture and AXI manager on the devices as described in HDL Language Support and Supported Third-Party Tools and Hardware. The support package contains the definition files for all supported boards. You must download the package before you can use FPGA data capture or AXI manager.

To download a support package:

• To download a support package, on the MATLAB Home tab, in the Environment section, click Add-Ons > Get Hardware Support Packages.

Set Up Hardware Board

Hardware boards require additional setup steps to connect to MATLAB and Simulink software. The Hardware Setup (SoC Blockset) tool guides you through the hardware setup process. Use this tool to configure a target hardware board and to use the FPGA data capture and AXI manager features.

To open the Hardware Setup tool:

• In the install window, at the end of the installation process, click the Setup Now button.

• After installing the support package, use Get and Manage Add-Ons. When the installation is complete, in the Installed section of the Add-Ons panel, click the Options button to the right of the support package that you want to set up. Then, select Setup.

  To open the Add-Ons panel, click the Add-Ons icon on the left sidebar.

For more information on the setup steps, see Set Up AMD FPGA and SoC Devices (SoC Blockset).